modes/asm/ghashv8-armx.pl: up to 90% performance improvement.
Reviewed-by: Matt Caswell <matt@openssl.org>
This commit is contained in:
Andy Polyakov
parent
be5a87a1b0
commit
7eeeb49e11
@ -16,12 +16,17 @@
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# other assembly modules. Just like aesv8-armx.pl this module
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# supports both AArch32 and AArch64 execution modes.
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#
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# July 2014
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#
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# Implement 2x aggregated reduction [see ghash-x86.pl for background
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# information].
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#
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# Current performance in cycles per processed byte:
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#
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# PMULL[2] 32-bit NEON(*)
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# Apple A7 1.76 5.62
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# Cortex-A53 1.45 8.39
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# Cortex-A57 2.22 7.61
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# Apple A7 0.92 5.62
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# Cortex-A53 1.01 8.39
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# Cortex-A57 1.17 7.61
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#
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# (*) presented for reference/comparison purposes;
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@ -45,7 +50,7 @@ $inc="x12";
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{
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my ($Xl,$Xm,$Xh,$IN)=map("q$_",(0..3));
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my ($t0,$t1,$t2,$t3,$H,$Hhl)=map("q$_",(8..14));
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my ($t0,$t1,$t2,$xC2,$H,$Hhl,$H2)=map("q$_",(8..14));
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$code=<<___;
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#include "arm_arch.h"
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@ -55,107 +60,108 @@ ___
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$code.=".arch armv8-a+crypto\n" if ($flavour =~ /64/);
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$code.=".fpu neon\n.code 32\n" if ($flavour !~ /64/);
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################################################################################
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# void gcm_init_v8(u128 Htable[16],const u64 H[2]);
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#
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# input: 128-bit H - secret parameter E(K,0^128)
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# output: precomputed table filled with degrees of twisted H;
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# H is twisted to handle reverse bitness of GHASH;
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# only few of 16 slots of Htable[16] are used;
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# data is opaque to outside world (which allows to
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# optimize the code independently);
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#
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$code.=<<___;
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.global gcm_init_v8
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.type gcm_init_v8,%function
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.align 4
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gcm_init_v8:
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vld1.64 {$t1},[x1] @ load H
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vmov.i8 $t0,#0xe1
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vld1.64 {$t1},[x1] @ load input H
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vmov.i8 $xC2,#0xe1
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vshl.i64 $xC2,$xC2,#57 @ 0xc2.0
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vext.8 $IN,$t1,$t1,#8
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vshl.i64 $t0,$t0,#57
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vshr.u64 $t2,$t0,#63
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vext.8 $t0,$t2,$t0,#8 @ t0=0xc2....01
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vshr.u64 $t2,$xC2,#63
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vdup.32 $t1,${t1}[1]
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vshr.u64 $t3,$IN,#63
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vext.8 $t0,$t2,$xC2,#8 @ t0=0xc2....01
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vshr.u64 $t2,$IN,#63
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vshr.s32 $t1,$t1,#31 @ broadcast carry bit
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vand $t3,$t3,$t0
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vand $t2,$t2,$t0
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vshl.i64 $IN,$IN,#1
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vext.8 $t3,$t3,$t3,#8
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vext.8 $t2,$t2,$t2,#8
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vand $t0,$t0,$t1
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vorr $IN,$IN,$t3 @ H<<<=1
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veor $IN,$IN,$t0 @ twisted H
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vst1.64 {$IN},[x0]
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vorr $IN,$IN,$t2 @ H<<<=1
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veor $H,$IN,$t0 @ twisted H
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vst1.64 {$H},[x0],#16 @ store Htable[0]
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@ calculate H^2
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vext.8 $t0,$H,$H,#8 @ Karatsuba pre-processing
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vpmull.p64 $Xl,$H,$H
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veor $t0,$t0,$H
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vpmull2.p64 $Xh,$H,$H
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vpmull.p64 $Xm,$t0,$t0
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vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
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veor $t2,$Xl,$Xh
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veor $Xm,$Xm,$t1
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veor $Xm,$Xm,$t2
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vpmull.p64 $t2,$Xl,$xC2 @ 1st phase
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vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
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vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
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veor $Xl,$Xm,$t2
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vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase
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vpmull.p64 $Xl,$Xl,$xC2
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veor $t2,$t2,$Xh
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veor $H2,$Xl,$t2
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vext.8 $t1,$H2,$H2,#8 @ Karatsuba pre-processing
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veor $t1,$t1,$H2
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vext.8 $Hhl,$t0,$t1,#8 @ pack Karatsuba pre-processed
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vst1.64 {$Hhl-$H2},[x0] @ store Htable[1..2]
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ret
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.size gcm_init_v8,.-gcm_init_v8
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___
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################################################################################
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# void gcm_gmult_v8(u64 Xi[2],const u128 Htable[16]);
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#
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# input: Xi - current hash value;
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# Htable - table precomputed in gcm_init_v8;
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# output: Xi - next hash value Xi;
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#
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$code.=<<___;
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.global gcm_gmult_v8
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.type gcm_gmult_v8,%function
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.align 4
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gcm_gmult_v8:
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vld1.64 {$t1},[$Xi] @ load Xi
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vmov.i8 $t3,#0xe1
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vld1.64 {$H},[$Htbl] @ load twisted H
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vshl.u64 $t3,$t3,#57
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vmov.i8 $xC2,#0xe1
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vld1.64 {$H-$Hhl},[$Htbl] @ load twisted H, ...
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vshl.u64 $xC2,$xC2,#57
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#ifndef __ARMEB__
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vrev64.8 $t1,$t1
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#endif
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vext.8 $Hhl,$H,$H,#8
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mov $len,#0
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vext.8 $IN,$t1,$t1,#8
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mov $inc,#0
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veor $Hhl,$Hhl,$H @ Karatsuba pre-processing
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mov $inp,$Xi
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b .Lgmult_v8
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.size gcm_gmult_v8,.-gcm_gmult_v8
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.global gcm_ghash_v8
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.type gcm_ghash_v8,%function
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.align 4
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gcm_ghash_v8:
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vld1.64 {$Xl},[$Xi] @ load [rotated] Xi
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subs $len,$len,#16
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vmov.i8 $t3,#0xe1
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mov $inc,#16
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vld1.64 {$H},[$Htbl] @ load twisted H
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cclr $inc,eq
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vext.8 $Xl,$Xl,$Xl,#8
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vshl.u64 $t3,$t3,#57
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vld1.64 {$t1},[$inp],$inc @ load [rotated] inp
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vext.8 $Hhl,$H,$H,#8
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#ifndef __ARMEB__
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vrev64.8 $Xl,$Xl
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vrev64.8 $t1,$t1
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#endif
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veor $Hhl,$Hhl,$H @ Karatsuba pre-processing
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vext.8 $IN,$t1,$t1,#8
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b .Loop_v8
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.align 4
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.Loop_v8:
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vext.8 $t2,$Xl,$Xl,#8
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veor $IN,$IN,$Xl @ inp^=Xi
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veor $t1,$t1,$t2 @ $t1 is rotated inp^Xi
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.Lgmult_v8:
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vpmull.p64 $Xl,$H,$IN @ H.lo·Xi.lo
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veor $t1,$t1,$IN @ Karatsuba pre-processing
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vpmull2.p64 $Xh,$H,$IN @ H.hi·Xi.hi
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subs $len,$len,#16
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vpmull.p64 $Xm,$Hhl,$t1 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
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cclr $inc,eq
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vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
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veor $t2,$Xl,$Xh
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veor $Xm,$Xm,$t1
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vld1.64 {$t1},[$inp],$inc @ load [rotated] inp
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veor $Xm,$Xm,$t2
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vpmull.p64 $t2,$Xl,$t3 @ 1st phase
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vpmull.p64 $t2,$Xl,$xC2 @ 1st phase of reduction
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vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
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vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
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#ifndef __ARMEB__
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vrev64.8 $t1,$t1
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#endif
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veor $Xl,$Xm,$t2
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vext.8 $IN,$t1,$t1,#8
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vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase
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vpmull.p64 $Xl,$Xl,$t3
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vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase of reduction
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vpmull.p64 $Xl,$Xl,$xC2
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veor $t2,$t2,$Xh
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veor $Xl,$Xl,$t2
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b.hs .Loop_v8
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#ifndef __ARMEB__
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vrev64.8 $Xl,$Xl
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@ -163,6 +169,168 @@ gcm_ghash_v8:
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vext.8 $Xl,$Xl,$Xl,#8
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vst1.64 {$Xl},[$Xi] @ write out Xi
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ret
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.size gcm_gmult_v8,.-gcm_gmult_v8
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___
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################################################################################
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# void gcm_ghash_v8(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);
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#
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# input: table precomputed in gcm_init_v8;
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# current hash value Xi;
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# pointer to input data;
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# length of input data in bytes, but divisible by block size;
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# output: next hash value Xi;
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#
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$code.=<<___;
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.global gcm_ghash_v8
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.type gcm_ghash_v8,%function
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.align 4
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gcm_ghash_v8:
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___
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$code.=<<___ if ($flavour !~ /64/);
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vstmdb sp!,{d8-d15} @ 32-bit ABI says so
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___
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$code.=<<___;
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vld1.64 {$Xl},[$Xi] @ load [rotated] Xi
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@ "[rotated]" means that
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@ loaded value would have
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@ to be rotated in order to
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@ make it appear as in
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@ alorithm specification
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subs $len,$len,#32 @ see if $len is 32 or larger
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mov $inc,#16 @ $inc is used as post-
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@ increment for input pointer;
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@ as loop is modulo-scheduled
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@ $inc is zeroed just in time
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@ to preclude oversteping
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@ inp[len], which means that
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@ last block[s] are actually
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@ loaded twice, but last
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@ copy is not processed
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vld1.64 {$H-$Hhl},[$Htbl],#32 @ load twisted H, ..., H^2
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vmov.i8 $xC2,#0xe1
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vld1.64 {$H2},[$Htbl]
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cclr $inc,eq @ is it time to zero $inc?
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vext.8 $Xl,$Xl,$Xl,#8 @ rotate Xi
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vld1.64 {$t0},[$inp],#16 @ load [rotated] I[0]
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vshl.u64 $xC2,$xC2,#57 @ compose 0xc2.0 constant
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#ifndef __ARMEB__
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vrev64.8 $t0,$t0
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vrev64.8 $Xl,$Xl
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#endif
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vext.8 $IN,$t0,$t0,#8 @ rotate I[0]
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b.lo .Lodd_tail_v8 @ $len was less than 32
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___
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{ my ($Xln,$Xmn,$Xhn,$In) = map("q$_",(4..7));
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#######
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# Xi+2 =[H*(Ii+1 + Xi+1)] mod P =
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# [(H*Ii+1) + (H*Xi+1)] mod P =
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# [(H*Ii+1) + H^2*(Ii+Xi)] mod P
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#
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$code.=<<___;
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vld1.64 {$t1},[$inp],$inc @ load [rotated] I[1]
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#ifndef __ARMEB__
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vrev64.8 $t1,$t1
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#endif
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vext.8 $In,$t1,$t1,#8
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veor $IN,$IN,$Xl @ I[i]^=Xi
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vpmull.p64 $Xln,$H,$In @ H·Ii+1
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veor $t1,$t1,$In @ Karatsuba pre-processing
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vpmull2.p64 $Xhn,$H,$In
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b .Loop_mod2x_v8
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.align 4
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.Loop_mod2x_v8:
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vext.8 $t2,$IN,$IN,#8
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subs $len,$len,#32 @ is there more data?
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vpmull.p64 $Xl,$H2,$IN @ H^2.lo·Xi.lo
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cclr $inc,lo @ is it time to zero $inc?
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vpmull.p64 $Xmn,$Hhl,$t1
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veor $t2,$t2,$IN @ Karatsuba pre-processing
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vpmull2.p64 $Xh,$H2,$IN @ H^2.hi·Xi.hi
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veor $Xl,$Xl,$Xln @ accumulate
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vpmull2.p64 $Xm,$Hhl,$t2 @ (H^2.lo+H^2.hi)·(Xi.lo+Xi.hi)
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vld1.64 {$t0},[$inp],$inc @ load [rotated] I[i+2]
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veor $Xh,$Xh,$Xhn
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cclr $inc,eq @ is it time to zero $inc?
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veor $Xm,$Xm,$Xmn
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vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
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veor $t2,$Xl,$Xh
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veor $Xm,$Xm,$t1
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vld1.64 {$t1},[$inp],$inc @ load [rotated] I[i+3]
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#ifndef __ARMEB__
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vrev64.8 $t0,$t0
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#endif
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veor $Xm,$Xm,$t2
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vpmull.p64 $t2,$Xl,$xC2 @ 1st phase of reduction
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#ifndef __ARMEB__
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vrev64.8 $t1,$t1
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#endif
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vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
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vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
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vext.8 $In,$t1,$t1,#8
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vext.8 $IN,$t0,$t0,#8
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veor $Xl,$Xm,$t2
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vpmull.p64 $Xln,$H,$In @ H·Ii+1
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veor $IN,$IN,$Xh @ accumulate $IN early
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vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase of reduction
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vpmull.p64 $Xl,$Xl,$xC2
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veor $IN,$IN,$t2
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veor $t1,$t1,$In @ Karatsuba pre-processing
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veor $IN,$IN,$Xl
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vpmull2.p64 $Xhn,$H,$In
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b.hs .Loop_mod2x_v8 @ there was at least 32 more bytes
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veor $Xh,$Xh,$t2
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vext.8 $IN,$t0,$t0,#8 @ re-construct $IN
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adds $len,$len,#32 @ re-construct $len
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veor $Xl,$Xl,$Xh @ re-construct $Xl
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b.eq .Ldone_v8 @ is $len zero?
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___
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}
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$code.=<<___;
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.Lodd_tail_v8:
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vext.8 $t2,$Xl,$Xl,#8
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veor $IN,$IN,$Xl @ inp^=Xi
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veor $t1,$t0,$t2 @ $t1 is rotated inp^Xi
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vpmull.p64 $Xl,$H,$IN @ H.lo·Xi.lo
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veor $t1,$t1,$IN @ Karatsuba pre-processing
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vpmull2.p64 $Xh,$H,$IN @ H.hi·Xi.hi
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vpmull.p64 $Xm,$Hhl,$t1 @ (H.lo+H.hi)·(Xi.lo+Xi.hi)
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vext.8 $t1,$Xl,$Xh,#8 @ Karatsuba post-processing
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veor $t2,$Xl,$Xh
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veor $Xm,$Xm,$t1
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veor $Xm,$Xm,$t2
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vpmull.p64 $t2,$Xl,$xC2 @ 1st phase of reduction
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vmov $Xh#lo,$Xm#hi @ Xh|Xm - 256-bit result
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vmov $Xm#hi,$Xl#lo @ Xm is rotated Xl
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veor $Xl,$Xm,$t2
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vext.8 $t2,$Xl,$Xl,#8 @ 2nd phase of reduction
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vpmull.p64 $Xl,$Xl,$xC2
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veor $t2,$t2,$Xh
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veor $Xl,$Xl,$t2
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.Ldone_v8:
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#ifndef __ARMEB__
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vrev64.8 $Xl,$Xl
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#endif
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vext.8 $Xl,$Xl,$Xl,#8
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vst1.64 {$Xl},[$Xi] @ write out Xi
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___
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$code.=<<___ if ($flavour !~ /64/);
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vldmia sp!,{d8-d15} @ 32-bit ABI says so
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___
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$code.=<<___;
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ret
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.size gcm_ghash_v8,.-gcm_ghash_v8
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___
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@ -230,7 +398,7 @@ if ($flavour =~ /64/) { ######## 64-bit code
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foreach(split("\n",$code)) {
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s/\b[wx]([0-9]+)\b/r$1/go; # new->old registers
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s/\bv([0-9])\.[12468]+[bsd]\b/q$1/go; # new->old registers
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s/\/\/\s?/@ /o; # new->old style commentary
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s/\/\/\s?/@ /o; # new->old style commentary
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# fix up remainig new-style suffixes
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s/\],#[0-9]+/]!/o;
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@ -242,7 +410,7 @@ if ($flavour =~ /64/) { ######## 64-bit code
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s/^(\s+)b\./$1b/o or
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s/^(\s+)ret/$1bx\tlr/o;
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print $_,"\n";
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print $_,"\n";
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}
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}
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