sparcv9cap.c: reiterate CPU detection logic.
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@ -232,13 +232,59 @@ _sparcv9_rdtick:
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.type _sparcv9_rdtick,#function
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.type _sparcv9_rdtick,#function
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.size _sparcv9_rdtick,.-_sparcv9_rdtick
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.size _sparcv9_rdtick,.-_sparcv9_rdtick
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! Probe and instrument VIS1 instruction. Output is number of cycles it
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! takes to execute rdtick and pair of VIS1 instructions. US-Tx VIS unit
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! is slow (documented to be 6 cycles on T2) and the core is in-order
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! single-issue, it should be possible to distinguish Tx reliably...
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! Observed return values are:
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!
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! UltraSPARC IIi 7
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! UltraSPARC III 7
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! UltraSPARC T1 24
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!
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! Numbers for T2 and SPARC64 V-VII are more than welcomed.
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!
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! It would be possible to detect specifically US-T1 by instrumenting
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! fmul8ulx16, which is emulated on T1 and as such accounts for quite
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! a lot of %tick-s, couple of thousand on Linux...
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.global _sparcv9_vis1_probe
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.global _sparcv9_vis1_probe
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.align 8
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.align 8
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_sparcv9_vis1_probe:
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_sparcv9_vis1_probe:
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.word 0x81b00c20 !fzeros %f0
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.word 0x91410000 !rd %tick,%o0
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add %sp,BIAS+2,%o0
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.word 0x81b00d80 !fxor %f0,%f0,%f0
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.word 0x85b08d82 !fxor %f2,%f2,%f2
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.word 0x93410000 !rd %tick,%o1
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.word 0x81b00d80 !fxor %f0,%f0,%f0
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.word 0x85b08d82 !fxor %f2,%f2,%f2
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.word 0x95410000 !rd %tick,%o2
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.word 0x81b00d80 !fxor %f0,%f0,%f0
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.word 0x85b08d82 !fxor %f2,%f2,%f2
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.word 0x97410000 !rd %tick,%o3
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.word 0x81b00d80 !fxor %f0,%f0,%f0
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.word 0x85b08d82 !fxor %f2,%f2,%f2
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.word 0x99410000 !rd %tick,%o4
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! calculate intervals
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sub %o1,%o0,%o0
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sub %o2,%o1,%o1
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sub %o3,%o2,%o2
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sub %o4,%o3,%o3
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! find minumum value
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cmp %o0,%o1
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.word 0x38680002 !bgu,a %xcc,.+8
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mov %o1,%o0
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cmp %o0,%o2
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.word 0x38680002 !bgu,a %xcc,.+8
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mov %o2,%o0
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cmp %o0,%o3
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.word 0x38680002 !bgu,a %xcc,.+8
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mov %o3,%o0
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! check for ASI_FP16_P is redundant...
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add %sp,BIAS+2,%o1
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retl
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retl
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.word 0xc19a1a40 !ldda [%o0]ASI_FP16_P,%f0
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.word 0xc19a5a40 !ldda [%o1]ASI_FP16_P,%f0
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.type _sparcv9_vis1_probe,#function
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.type _sparcv9_vis1_probe,#function
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.size _sparcv9_vis1_probe,.-_sparcv9_vis1_probe
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.size _sparcv9_vis1_probe,.-_sparcv9_vis1_probe
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@ -27,7 +27,7 @@ int bn_mul_mont(BN_ULONG *rp, const BN_ULONG *ap, const BN_ULONG *bp, const BN_U
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}
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}
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unsigned long _sparcv9_rdtick(void);
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unsigned long _sparcv9_rdtick(void);
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void _sparcv9_vis1_probe(void);
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unsigned long _sparcv9_vis1_probe(void);
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unsigned long OPENSSL_rdtsc(void)
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unsigned long OPENSSL_rdtsc(void)
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{
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{
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@ -175,16 +175,30 @@ void OPENSSL_cpuid_setup(void)
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common_act.sa_handler = common_handler;
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common_act.sa_handler = common_handler;
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common_act.sa_mask = all_masked;
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common_act.sa_mask = all_masked;
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sigaction(SIGILL,&common_act,&ill_oact);
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if (sigsetjmp(common_jmp,0) == 0)
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{
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_sparcv9_rdtick();
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OPENSSL_sparcv9cap_P &= ~SPARCV9_TICK_PRIVILEGED;
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}
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else
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{
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/* This happens on US-I&II, which have working VIS1
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* and fast FPU... In other words we are done... */
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OPENSSL_sparcv9cap_P |= SPARCV9_TICK_PRIVILEGED;
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sigaction(SIGILL,&ill_oact,NULL);
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sigprocmask(SIG_SETMASK,&oset,NULL);
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return;
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}
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sigaction(SIGILL,&ill_oact,NULL);
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sigaction(SIGILL,&common_act,&ill_oact);
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sigaction(SIGILL,&common_act,&ill_oact);
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sigaction(SIGBUS,&common_act,&bus_oact);/* T1 fails 16-bit ldda */
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sigaction(SIGBUS,&common_act,&bus_oact);/* T1 fails 16-bit ldda */
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if ((sig=sigsetjmp(common_jmp,0)) == 0)
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if ((sig=sigsetjmp(common_jmp,0)) == 0)
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{
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{
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_sparcv9_vis1_probe();
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/* see sparccpud.S for details... */
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OPENSSL_sparcv9cap_P |= SPARCV9_VIS1;
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if (_sparcv9_vis1_probe() >= 12)
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}
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OPENSSL_sparcv9cap_P &= ~SPARCV9_VIS1;
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else if (sig == SIGBUS) /* T1 fails 16-bit ldda */
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{
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OPENSSL_sparcv9cap_P &= ~SPARCV9_PREFER_FPU;
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}
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}
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else
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else
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{
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{
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@ -193,18 +207,6 @@ void OPENSSL_cpuid_setup(void)
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sigaction(SIGBUS,&bus_oact,NULL);
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sigaction(SIGBUS,&bus_oact,NULL);
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sigaction(SIGILL,&ill_oact,NULL);
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sigaction(SIGILL,&ill_oact,NULL);
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sigaction(SIGILL,&common_act,&ill_oact);
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if (sigsetjmp(common_jmp,0) == 0)
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{
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_sparcv9_rdtick();
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OPENSSL_sparcv9cap_P &= ~SPARCV9_TICK_PRIVILEGED;
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}
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else
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{
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OPENSSL_sparcv9cap_P |= SPARCV9_TICK_PRIVILEGED;
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}
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sigaction(SIGILL,&ill_oact,NULL);
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sigprocmask(SIG_SETMASK,&oset,NULL);
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sigprocmask(SIG_SETMASK,&oset,NULL);
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}
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}
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