sha1-sparcv9a.pl: fix bug in commentary section.
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@ -112,8 +112,9 @@ ___
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# virtually uniform performance of ~9.3 cycles per SHA1 round. Timings
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# mentioned above are theoretical lower limits. Real-life performance
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# was measured to be 6.6 cycles per SHA1 round on USIIi and 8.3 on
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# USIII. The latter means that processor manual must have an error in
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# instruction latency table or there is some unmentioned shortcut...
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# USIII. The latter is lower than half-round VIS timing, because there
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# are 16 Xupdate-free rounds, which "push down" average theoretical
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# timing to 8 cycles...
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}
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# The reference Xupdate procedure is then "strained" over *pairs* of
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