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OPENSSL_ia32cap.pod update.

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Andy Polyakov 2006-10-23 07:44:51 +00:00
parent a6efc2d1b8
commit 544d845585
1 changed files with 7 additions and 6 deletions
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doc/crypto/OPENSSL_ia32cap.pod
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@ -17,18 +17,19 @@ register after executing CPUID instruction with EAX=1 input value (see
Intel Application Note #241618). Naturally it's meaningful on IA-32[E]
platforms only. The variable is normally set up automatically upon
toolkit initialization, but can be manipulated afterwards to modify
crypto library behaviour. For the moment of this writing three bits are
crypto library behaviour. For the moment of this writing five bits are
significant, namely bit #28 denoting Hyperthreading, which is used to
distinguish Intel P4 core, bit #26 denoting SSE2 support, and bit #4
denoting presence of Time-Stamp Counter. Clearing bit #26 at run-time
for example disables high-performance SSE2 code present in the crypto
distinguish Intel P4 core, bit #26 denoting SSE2 support, bit #25
denoting SSE support, bit #23 denoting MMX support, and bit #4 denoting
presence of Time-Stamp Counter. Clearing bit #26 at run-time for
example disables high-performance SSE2 code present in the crypto
library. You might have to do this if target OpenSSL application is
executed on SSE2 capable CPU, but under control of OS which does not
support SSE2 extentions. Even though you can manipulate the value
programmatically, you most likely will find it more appropriate to set
up an environment variable with the same name prior starting target
application, e.g. 'env OPENSSL_ia32cap=0x10 apps/openssl', to achieve
same effect without modifying the application source code.
application, e.g. 'env OPENSSL_ia32cap=0x12800010 apps/openssl', to
achieve same effect without modifying the application source code.
Alternatively you can reconfigure the toolkit with no-sse2 option and
recompile.