This update implements following improvements.
1. Original submission required minor modification to RC4_set_key, which we don't want to tolerate and therefore we fix assembler instead. 2. Eliminate remaining byte-order dependence [look for RC4_BIG_ENDIAN]. 3. Eliminate logical error [when key->x is referred prior key is verified]. 4. HP-UX assembler puked on MODSCHED_RC4 macro with "syntax error," macro has to be splitted in two. 5. Deploy parallel compare in function prologue. 6. Eliminate redundant instuctions and nops. 7. Eliminate assembler warnings.
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02703c74a4
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@ -194,21 +194,13 @@ $threshold = (3 * ($phases * ($unroll_count + 1)) + 7);
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sub I {
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local *code = shift;
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local $format = shift;
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local $a0 = shift;
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local $a1 = shift;
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local $a2 = shift;
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local $a3 = shift;
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$code .= sprintf ("\t\t".$format."\n", $a0, $a1, $a2, $a3);
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$code .= sprintf ("\t\t".$format."\n", @_);
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}
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sub P {
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local *code = shift;
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local $format = shift;
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local $a0 = shift;
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local $a1 = shift;
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local $a2 = shift;
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local $a3 = shift;
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$code .= sprintf ($format."\n", $a0, $a1, $a2, $a3);
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$code .= sprintf ($format."\n", @_);
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}
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sub STOP {
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@ -239,6 +231,10 @@ sub emit_body {
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___
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if (($p & 0xf) == 0) {
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$c.="#ifdef RC4_BIG_ENDIAN\n";
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&I(\$c,"shr.u OutWord[%u] = OutWord[%u], 32;;",
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$iw1 % $NOutWord, $iw1 % $NOutWord);
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$c.="#endif\n";
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&I(\$c, "st4 [OutPtr] = OutWord[%u], 4", $iw1 % $NOutWord);
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return;
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}
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@ -311,6 +307,7 @@ ___
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&I(\$bypass, "add J = J, SI[%u]", $i1 % $NSI);
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&I(\$bypass, "mov SI[%u] = SI[%u]", $i0 % $NSI, $i1 % $NSI);
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&I(\$bypass, "br.sptk.many .rc4Resume%u\n", $label);
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&I(\$bypass, ";;");
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}
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}
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@ -394,10 +391,11 @@ $code=<<___;
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/* Define a macro for the bit number of the n-th byte: */
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#ifdef L_ENDIAN
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# define BYTE_POS(n) (8 * (n))
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#else
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#if defined(_HPUX_SOURCE) || defined(B_ENDIAN)
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# define RC4_BIG_ENDIAN
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# define BYTE_POS(n) (56 - (8 * (n)))
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#else
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# define BYTE_POS(n) (8 * (n))
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#endif
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/*
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@ -406,8 +404,9 @@ $code=<<___;
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will never be taken since regardless of the number of bytes because
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the epilogue count is 4.
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*/
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#define MODSCHED_RC4(label) \\
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/* MODSCHED_RC4 macro was split to _PROLOGUE and _LOOP, because HP-UX
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assembler failed on original macro with syntax error. <appro> */
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#define MODSCHED_RC4_PROLOGUE \\
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{ \\
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ld1 Data[0] = [InPtr], 1; \\
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add IFinal = 1, I[1]; \\
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@ -421,8 +420,9 @@ $code=<<___;
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{ \\
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add J = J, SI[0]; \\
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zxt1 I[0] = IFinal; \\
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br.cexit.spnt.few label; /* never taken */ \\
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} ;; \\
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br.cexit.spnt.few .+16; /* never taken */ \\
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} ;;
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#define MODSCHED_RC4_LOOP(label) \\
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label: \\
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{ .mmi; \\
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(pComputeI) ld1 Data[0] = [InPtr], 1; \\
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@ -476,63 +476,42 @@ RC4:
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OutWord[2]
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.rotp pPhase[4]
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#ifdef _LP64
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add InPrefetch = 0, InputBuffer
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nop 0x0
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}
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#else
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ADDP InputBuffer = 0, InputBuffer
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ADDP StateTable = 0, StateTable
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}
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;;
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{
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ADDP InPrefetch = 0, InputBuffer
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ADDP OutputBuffer = 0, OutputBuffer
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nop 0x0
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ADDP KTable = 0, StateTable
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}
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{
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.mmi
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ADDP InPtr = 0, InputBuffer
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ADDP OutPtr = 0, OutputBuffer
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mov RetVal = r0
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}
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#endif
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;;
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{
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.mmi
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lfetch.nt1 [InPrefetch], 0x80
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LKEY I[1] = [StateTable], SZ
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mov OutPrefetch = OutputBuffer
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} ;;
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{
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.mii
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nop 0x0
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nop 0x0
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mov RetVal = r0
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ADDP OutPrefetch = 0, OutputBuffer
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}
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{ // Return 0 if the input length is nonsensical
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.mib
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nop 0x0
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cmp.ge L_NOK, L_OK = r0, DataLen
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ADDP StateTable = 0, StateTable
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cmp.ge.unc L_NOK, L_OK = r0, DataLen
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(L_NOK) br.ret.sptk.few rp
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}
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;;
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{
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.mib
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nop 0x0
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cmp.eq L_NOK, L_OK = r0, InputBuffer
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cmp.eq.or L_NOK, L_OK = r0, InPtr
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cmp.eq.or L_NOK, L_OK = r0, OutPtr
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nop 0x0
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}
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{
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.mib
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cmp.eq.or L_NOK, L_OK = r0, StateTable
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nop 0x0
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(L_NOK) br.ret.sptk.few rp
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}
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;;
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{
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.mib
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nop 0x0
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cmp.eq L_NOK, L_OK = r0, OutputBuffer
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(L_NOK) br.ret.sptk.few rp
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}
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;;
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{
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.mib
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nop 0x0
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cmp.eq L_NOK, L_OK = r0, StateTable
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(L_NOK) br.ret.sptk.few rp
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}
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LKEY I[1] = [KTable], SZ
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/* Prefetch the state-table. It contains 256 elements of size SZ */
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#if SZ == 1
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@ -568,8 +547,12 @@ RC4:
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lfetch.fault.nt1 [tmp0], -256 // 3
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lfetch.fault.nt1 [tmp1], -256;;
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#endif
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{
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.mii
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lfetch.fault.nt1 [tmp0] // 1
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add I[1]=1,I[1];;
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zxt1 I[1]=I[1]
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}
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{
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.mmi
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lfetch.nt1 [InPrefetch], 0x80
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@ -580,19 +563,13 @@ RC4:
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{
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.mmi
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lfetch.excl.nt1 [OutPrefetch], 0x80
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LKEY J = [StateTable], SZ
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ADDP EndPtr = DataLen, InputBuffer
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LKEY J = [KTable], SZ
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ADDP EndPtr = DataLen, InPtr
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} ;;
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{
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.mmi
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mov InPtr = InputBuffer
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mov OutPtr = OutputBuffer
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ADDP EndPtr = -1, EndPtr // Make it point to
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// last data byte.
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} ;;
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{
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.mii
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mov KTable = StateTable
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mov One = 1
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.save ar.lc, LCSave
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mov LCSave = ar.lc
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@ -614,6 +591,7 @@ RC4:
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} ;;
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{
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.mmb
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.pred.rel "mutex",pUnaligned,pAligned
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(pUnaligned) add Remainder = -1, Remainder
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(pAligned) sub Remainder = EndPtr, InPtr
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(pAligned) br.cond.dptk.many .rc4Aligned
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@ -628,7 +606,8 @@ RC4:
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/* Do the initial few bytes via the compact, modulo-scheduled loop
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until the output pointer is 8-byte-aligned. */
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MODSCHED_RC4(.RC4AlignLoop)
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MODSCHED_RC4_PROLOGUE
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MODSCHED_RC4_LOOP(.RC4AlignLoop)
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{
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.mib
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@ -671,13 +650,7 @@ RC4:
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} ;;
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{
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.mmi
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getf.sig LoopCount = f6 // M2 5 cyc
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nop 0x0
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nop 0x0
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} ;;
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{
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.mmi
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nop 0x0
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getf.sig LoopCount = f6;; // M2 5 cyc
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nop 0x0
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shr.u LoopCount = LoopCount, 4
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} ;;
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@ -747,32 +720,26 @@ $code.=<<___;
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/* Do the remaining bytes via the compact, modulo-scheduled loop */
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MODSCHED_RC4(.RC4RestLoop)
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{
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.mmi
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nop 0x0
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nop 0x0
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zxt1 IFinal = IFinal
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} ;;
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MODSCHED_RC4_PROLOGUE
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MODSCHED_RC4_LOOP(.RC4RestLoop)
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.rc4Complete:
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{
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.mmi
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ADDP KTable = -2*SZ, KTable ;;
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SKEY [KTable] = IFinal, SZ
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add KTable = -SZ, KTable
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add IFinal = -1, IFinal
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mov ar.lc = LCSave
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} ;;
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{
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.mii
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nop 0x0
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nop 0x0
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add RetVal = 1, r0
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}
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SKEY [KTable] = J,-SZ
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zxt1 IFinal = IFinal
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mov pr = PRSave, 0x1FFFF
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} ;;
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{
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.mib
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SKEY [KTable] = J
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mov pr = PRSave, 0x1FFFF
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SKEY [KTable] = IFinal
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add RetVal = 1, r0
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br.ret.sptk.few rp
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} ;;
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___
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