ARM assembly pack: SHA update from master.
This commit is contained in:
Andy Polyakov
parent
b76310ba74
commit
422c8c36e5
@ -21,15 +21,15 @@
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# February 2011.
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#
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# Profiler-assisted and platform-specific optimization resulted in 16%
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# improvement on Cortex A8 core and ~17 cycles per processed byte.
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# improvement on Cortex A8 core and ~16.4 cycles per processed byte.
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while (($output=shift) && ($output!~/^\w[\w\-]*\.\w+$/)) {}
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open STDOUT,">$output";
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$ctx="r0"; $t0="r0";
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$inp="r1"; $t3="r1";
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$inp="r1"; $t4="r1";
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$len="r2"; $t1="r2";
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$T1="r3";
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$T1="r3"; $t3="r3";
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$A="r4";
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$B="r5";
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$C="r6";
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@ -52,71 +52,90 @@ my ($i,$a,$b,$c,$d,$e,$f,$g,$h) = @_;
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$code.=<<___ if ($i<16);
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#if __ARM_ARCH__>=7
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ldr $T1,[$inp],#4
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@ ldr $t1,[$inp],#4 @ $i
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# if $i==15
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str $inp,[sp,#17*4] @ make room for $t4
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# endif
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mov $t0,$e,ror#$Sigma1[0]
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add $a,$a,$t2 @ h+=Maj(a,b,c) from the past
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rev $t1,$t1
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eor $t0,$t0,$e,ror#$Sigma1[1]
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#else
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ldrb $T1,[$inp,#3] @ $i
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@ ldrb $t1,[$inp,#3] @ $i
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add $a,$a,$t2 @ h+=Maj(a,b,c) from the past
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ldrb $t2,[$inp,#2]
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ldrb $t1,[$inp,#1]
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ldrb $t0,[$inp],#4
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orr $T1,$T1,$t2,lsl#8
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orr $T1,$T1,$t1,lsl#16
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orr $T1,$T1,$t0,lsl#24
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ldrb $t0,[$inp,#1]
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orr $t1,$t1,$t2,lsl#8
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ldrb $t2,[$inp],#4
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orr $t1,$t1,$t0,lsl#16
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# if $i==15
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str $inp,[sp,#17*4] @ make room for $t4
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# endif
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mov $t0,$e,ror#$Sigma1[0]
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orr $t1,$t1,$t2,lsl#24
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eor $t0,$t0,$e,ror#$Sigma1[1]
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#endif
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___
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$code.=<<___;
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mov $t0,$e,ror#$Sigma1[0]
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ldr $t2,[$Ktbl],#4 @ *K256++
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eor $t0,$t0,$e,ror#$Sigma1[1]
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add $h,$h,$t1 @ h+=X[i]
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str $t1,[sp,#`$i%16`*4]
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eor $t1,$f,$g
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#if $i>=16
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add $T1,$T1,$t3 @ from BODY_16_xx
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#elif __ARM_ARCH__>=7 && defined(__ARMEL__)
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rev $T1,$T1
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#endif
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#if $i==15
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str $inp,[sp,#17*4] @ leave room for $t3
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#endif
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eor $t0,$t0,$e,ror#$Sigma1[2] @ Sigma1(e)
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and $t1,$t1,$e
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str $T1,[sp,#`$i%16`*4]
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add $T1,$T1,$t0
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add $h,$h,$t0 @ h+=Sigma1(e)
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eor $t1,$t1,$g @ Ch(e,f,g)
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add $T1,$T1,$h
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mov $h,$a,ror#$Sigma0[0]
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add $T1,$T1,$t1
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eor $h,$h,$a,ror#$Sigma0[1]
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add $T1,$T1,$t2
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eor $h,$h,$a,ror#$Sigma0[2] @ Sigma0(a)
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#if $i>=15
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ldr $t3,[sp,#`($i+2)%16`*4] @ from BODY_16_xx
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add $h,$h,$t2 @ h+=K256[i]
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mov $t0,$a,ror#$Sigma0[0]
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add $h,$h,$t1 @ h+=Ch(e,f,g)
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#if $i==31
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and $t2,$t2,#0xff
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cmp $t2,#0xf2 @ done?
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#endif
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orr $t0,$a,$b
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and $t1,$a,$b
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and $t0,$t0,$c
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add $h,$h,$T1
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orr $t0,$t0,$t1 @ Maj(a,b,c)
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add $d,$d,$T1
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add $h,$h,$t0
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#if $i<15
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# if __ARM_ARCH__>=7
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ldr $t1,[$inp],#4 @ prefetch
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# else
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ldrb $t1,[$inp,#3]
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# endif
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eor $t2,$a,$b @ a^b, b^c in next round
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#else
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ldr $t1,[sp,#`($i+2)%16`*4] @ from future BODY_16_xx
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eor $t2,$a,$b @ a^b, b^c in next round
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ldr $t4,[sp,#`($i+15)%16`*4] @ from future BODY_16_xx
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#endif
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eor $t0,$a,ror#$Sigma0[1]
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and $t3,$t3,$t2 @ (b^c)&=(a^b)
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add $d,$d,$h @ d+=h
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eor $t0,$a,ror#$Sigma0[2] @ Sigma0(a)
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eor $t3,$t3,$b @ Maj(a,b,c)
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add $h,$h,$t0 @ h+=Sigma0(a)
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@ add $h,$h,$t3 @ h+=Maj(a,b,c)
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___
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($t2,$t3)=($t3,$t2);
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}
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sub BODY_16_XX {
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my ($i,$a,$b,$c,$d,$e,$f,$g,$h) = @_;
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$code.=<<___;
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@ ldr $t3,[sp,#`($i+1)%16`*4] @ $i
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ldr $t2,[sp,#`($i+14)%16`*4]
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mov $t0,$t3,ror#$sigma0[0]
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ldr $T1,[sp,#`($i+0)%16`*4]
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eor $t0,$t0,$t3,ror#$sigma0[1]
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ldr $t1,[sp,#`($i+9)%16`*4]
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eor $t0,$t0,$t3,lsr#$sigma0[2] @ sigma0(X[i+1])
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mov $t3,$t2,ror#$sigma1[0]
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add $T1,$T1,$t0
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eor $t3,$t3,$t2,ror#$sigma1[1]
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add $T1,$T1,$t1
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eor $t3,$t3,$t2,lsr#$sigma1[2] @ sigma1(X[i+14])
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@ add $T1,$T1,$t3
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@ ldr $t1,[sp,#`($i+1)%16`*4] @ $i
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@ ldr $t4,[sp,#`($i+14)%16`*4]
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mov $t0,$t1,ror#$sigma0[0]
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add $a,$a,$t2 @ h+=Maj(a,b,c) from the past
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mov $t2,$t4,ror#$sigma1[0]
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eor $t0,$t0,$t1,ror#$sigma0[1]
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eor $t2,$t2,$t4,ror#$sigma1[1]
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eor $t0,$t0,$t1,lsr#$sigma0[2] @ sigma0(X[i+1])
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ldr $t1,[sp,#`($i+0)%16`*4]
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eor $t2,$t2,$t4,lsr#$sigma1[2] @ sigma1(X[i+14])
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ldr $t4,[sp,#`($i+9)%16`*4]
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add $t2,$t2,$t0
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mov $t0,$e,ror#$Sigma1[0] @ from BODY_00_15
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add $t1,$t1,$t2
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eor $t0,$t0,$e,ror#$Sigma1[1] @ from BODY_00_15
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add $t1,$t1,$t4 @ X[i]
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___
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&BODY_00_15(@_);
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}
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@ -158,35 +177,41 @@ sha256_block_data_order:
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sub $Ktbl,r3,#256 @ K256
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sub sp,sp,#16*4 @ alloca(X[16])
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.Loop:
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# if __ARM_ARCH__>=7
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ldr $t1,[$inp],#4
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# else
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ldrb $t1,[$inp,#3]
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# endif
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eor $t3,$B,$C @ magic
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eor $t2,$t2,$t2
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___
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for($i=0;$i<16;$i++) { &BODY_00_15($i,@V); unshift(@V,pop(@V)); }
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$code.=".Lrounds_16_xx:\n";
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for (;$i<32;$i++) { &BODY_16_XX($i,@V); unshift(@V,pop(@V)); }
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$code.=<<___;
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and $t2,$t2,#0xff
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cmp $t2,#0xf2
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ldreq $t3,[sp,#16*4] @ pull ctx
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bne .Lrounds_16_xx
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ldr $T1,[sp,#16*4] @ pull ctx
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ldr $t0,[$T1,#0]
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ldr $t1,[$T1,#4]
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ldr $t2,[$T1,#8]
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add $A,$A,$t2 @ h+=Maj(a,b,c) from the past
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ldr $t0,[$t3,#0]
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ldr $t1,[$t3,#4]
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ldr $t2,[$t3,#8]
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add $A,$A,$t0
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ldr $t0,[$T1,#12]
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ldr $t0,[$t3,#12]
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add $B,$B,$t1
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ldr $t1,[$T1,#16]
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ldr $t1,[$t3,#16]
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add $C,$C,$t2
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ldr $t2,[$T1,#20]
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ldr $t2,[$t3,#20]
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add $D,$D,$t0
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ldr $t0,[$T1,#24]
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ldr $t0,[$t3,#24]
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add $E,$E,$t1
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ldr $t1,[$T1,#28]
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ldr $t1,[$t3,#28]
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add $F,$F,$t2
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ldr $inp,[sp,#17*4] @ pull inp
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ldr $t2,[sp,#18*4] @ pull inp+len
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add $G,$G,$t0
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add $H,$H,$t1
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stmia $T1,{$A,$B,$C,$D,$E,$F,$G,$H}
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stmia $t3,{$A,$B,$C,$D,$E,$F,$G,$H}
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cmp $inp,$t2
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sub $Ktbl,$Ktbl,#256 @ rewind Ktbl
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bne .Loop
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@ -1,7 +1,7 @@
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#!/usr/bin/env perl
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# ====================================================================
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# Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
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# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
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# project. The module is, however, dual licensed under OpenSSL and
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# details see http://www.openssl.org/~appro/cryptogams/.
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@ -26,7 +26,24 @@
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# March 2011.
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#
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# Add NEON implementation. On Cortex A8 it was measured to process
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# one byte in 25.5 cycles or 47% faster than integer-only code.
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# one byte in 23.3 cycles or ~60% faster than integer-only code.
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# August 2012.
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#
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# Improve NEON performance by 12% on Snapdragon S4. In absolute
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# terms it's 22.6 cycles per byte, which is disappointing result.
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# Technical writers asserted that 3-way S4 pipeline can sustain
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# multiple NEON instructions per cycle, but dual NEON issue could
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# not be observed, and for NEON-only sequences IPC(*) was found to
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# be limited by 1:-( 0.33 and 0.66 were measured for sequences with
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# ILPs(*) of 1 and 2 respectively. This in turn means that you can
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# even find yourself striving, as I did here, for achieving IPC
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# adequate to one delivered by Cortex A8 [for reference, it's
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# 0.5 for ILP of 1, and 1 for higher ILPs].
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#
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# (*) ILP, instruction-level parallelism, how many instructions
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# *can* execute at the same time. IPC, instructions per cycle,
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# indicates how many instructions actually execute.
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# Byte order [in]dependence. =========================================
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#
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@ -457,40 +474,40 @@ $code.=<<___ if ($i<16 || $i&1);
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vld1.64 {@X[$i%16]},[$inp]! @ handles unaligned
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#endif
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vshr.u64 $t1,$e,#@Sigma1[1]
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#if $i>0
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vadd.i64 $a,$Maj @ h+=Maj from the past
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#endif
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vshr.u64 $t2,$e,#@Sigma1[2]
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___
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$code.=<<___;
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vld1.64 {$K},[$Ktbl,:64]! @ K[i++]
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vsli.64 $t0,$e,#`64-@Sigma1[0]`
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vsli.64 $t1,$e,#`64-@Sigma1[1]`
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vmov $Ch,$e
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vsli.64 $t2,$e,#`64-@Sigma1[2]`
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#if $i<16 && defined(__ARMEL__)
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vrev64.8 @X[$i],@X[$i]
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#endif
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vadd.i64 $T1,$K,$h
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veor $Ch,$f,$g
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veor $t0,$t1
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vand $Ch,$e
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veor $t0,$t2 @ Sigma1(e)
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veor $Ch,$g @ Ch(e,f,g)
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vadd.i64 $T1,$t0
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veor $t1,$t0
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vbsl $Ch,$f,$g @ Ch(e,f,g)
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vshr.u64 $t0,$a,#@Sigma0[0]
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vadd.i64 $T1,$Ch
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veor $t2,$t1 @ Sigma1(e)
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vadd.i64 $T1,$Ch,$h
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vshr.u64 $t1,$a,#@Sigma0[1]
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vshr.u64 $t2,$a,#@Sigma0[2]
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vsli.64 $t0,$a,#`64-@Sigma0[0]`
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vadd.i64 $T1,$t2
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vshr.u64 $t2,$a,#@Sigma0[2]
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vadd.i64 $K,@X[$i%16]
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vsli.64 $t1,$a,#`64-@Sigma0[1]`
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veor $Maj,$a,$b
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vsli.64 $t2,$a,#`64-@Sigma0[2]`
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vadd.i64 $T1,@X[$i%16]
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vorr $Maj,$a,$c
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vand $Ch,$a,$c
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veor $h,$t0,$t1
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vand $Maj,$b
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vadd.i64 $T1,$K
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vbsl $Maj,$c,$b @ Maj(a,b,c)
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veor $h,$t2 @ Sigma0(a)
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vorr $Maj,$Ch @ Maj(a,b,c)
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vadd.i64 $h,$T1
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vadd.i64 $d,$T1
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vadd.i64 $h,$Maj
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vadd.i64 $Maj,$T1
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@ vadd.i64 $h,$Maj
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___
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}
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@ -508,6 +525,7 @@ $i /= 2;
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$code.=<<___;
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vshr.u64 $t0,@X[($i+7)%8],#@sigma1[0]
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vshr.u64 $t1,@X[($i+7)%8],#@sigma1[1]
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vadd.i64 @_[0],d30 @ h+=Maj from the past
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vshr.u64 $s1,@X[($i+7)%8],#@sigma1[2]
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vsli.64 $t0,@X[($i+7)%8],#`64-@sigma1[0]`
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vext.8 $s0,@X[$i%8],@X[($i+1)%8],#8 @ X[i+1]
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@ -554,6 +572,7 @@ for(;$i<32;$i++) { &NEON_16_79($i,@V); unshift(@V,pop(@V)); }
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$code.=<<___;
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bne .L16_79_neon
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vadd.i64 $A,d30 @ h+=Maj from the past
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vldmia $ctx,{d24-d31} @ load context to temp
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vadd.i64 q8,q12 @ vectorized accumulate
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vadd.i64 q9,q13
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