Modulo-schedule loops in sparcv9a-mont.pl. Overall improvement factor
over 0.9.8 is up to 3x on USI&II cores and up to 80% - on USIII&IV.
This commit is contained in:
parent
1c3d2b94be
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2e21922eb6
@ -2,8 +2,9 @@
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# ====================================================================
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# Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
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# project. Rights for redistribution and usage in source and binary
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# forms are granted according to the OpenSSL license.
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# project. The module is, however, dual licensed under OpenSSL and
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# details see http://www.openssl.org/~appro/cryptogams/.
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# ====================================================================
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# October 2005
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@ -47,6 +48,15 @@
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# noticeable(!) improvement);
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# - dedicated squaring procedure[?];
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######################################################################
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# November 2006
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#
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# Modulo-scheduled inner loops allow to interleave floating point and
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# integer instructions and minimize Read-After-Write penalties. This
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# results in *further* 20-50% perfromance improvement [depending on
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# key length, more for longer keys] on USI&II cores and 30-80% - on
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# USIII&IV.
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$fname="bn_mul_mont_fpu";
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$bits=32;
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for (@ARGV) { $bits=64 if (/\-m64/ || /\-xarch\=v9/); }
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@ -261,34 +271,13 @@ $fname:
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fdtox $nlod,$nlod
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std $nloa,[%sp+$bias+$frame+0]
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std $nlob,[%sp+$bias+$frame+8]
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std $nloc,[%sp+$bias+$frame+16]
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std $nlod,[%sp+$bias+$frame+24]
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ldx [%sp+$bias+$frame+0],%o0
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ldx [%sp+$bias+$frame+8],%o1
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ldx [%sp+$bias+$frame+16],%o2
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ldx [%sp+$bias+$frame+24],%o3
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srlx %o0,16,%o7
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add %o7,%o1,%o1
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srlx %o1,16,%o7
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add %o7,%o2,%o2
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srlx %o2,16,%o7
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add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
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!and %o0,$mask,%o0
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!and %o1,$mask,%o1
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!and %o2,$mask,%o2
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!sllx %o1,16,%o1
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!sllx %o2,32,%o2
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!sllx %o3,48,%o7
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!or %o1,%o0,%o0
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!or %o2,%o0,%o0
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!or %o7,%o0,%o0 ! 64-bit result
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srlx %o3,16,%g1 ! 34-bit carry
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add $j,8,$j
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std $nlob,[%sp+$bias+$frame+8]
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add $ap,$j,%o4
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std $nloc,[%sp+$bias+$frame+16]
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add $np,$j,%o5
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std $nlod,[%sp+$bias+$frame+24]
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ld [%o4+0],$alo_ ! load a[j] as pair of 32-bit words
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fzeros $alo
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ld [%o4+4],$ahi_
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@ -303,24 +292,46 @@ $fname:
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fxtod $nlo,$nlo
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fxtod $nhi,$nhi
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std $alo,[$ap_l+$j] ! save smashed ap[j] in double format
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ldx [%sp+$bias+$frame+0],%o0
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fmuld $alo,$ba,$aloa
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std $ahi,[$ap_h+$j]
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ldx [%sp+$bias+$frame+8],%o1
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fmuld $nlo,$na,$nloa
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std $nlo,[$np_l+$j] ! save smashed np[j] in double format
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ldx [%sp+$bias+$frame+16],%o2
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fmuld $alo,$bb,$alob
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std $nhi,[$np_h+$j]
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ldx [%sp+$bias+$frame+24],%o3
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fmuld $nlo,$nb,$nlob
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srlx %o0,16,%o7
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std $alo,[$ap_l+$j] ! save smashed ap[j] in double format
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fmuld $alo,$bc,$aloc
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add %o7,%o1,%o1
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std $ahi,[$ap_h+$j]
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faddd $aloa,$nloa,$nloa
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fmuld $nlo,$nc,$nloc
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srlx %o1,16,%o7
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std $nlo,[$np_l+$j] ! save smashed np[j] in double format
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fmuld $alo,$bd,$alod
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add %o7,%o2,%o2
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std $nhi,[$np_h+$j]
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faddd $alob,$nlob,$nlob
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fmuld $nlo,$nd,$nlod
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srlx %o2,16,%o7
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fmuld $ahi,$ba,$ahia
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add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
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faddd $aloc,$nloc,$nloc
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fmuld $nhi,$na,$nhia
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!and %o0,$mask,%o0
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!and %o1,$mask,%o1
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!and %o2,$mask,%o2
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!sllx %o1,16,%o1
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!sllx %o2,32,%o2
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!sllx %o3,48,%o7
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!or %o1,%o0,%o0
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!or %o2,%o0,%o0
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!or %o7,%o0,%o0 ! 64-bit result
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srlx %o3,16,%g1 ! 34-bit carry
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fmuld $ahi,$bb,$ahib
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faddd $alod,$nlod,$nlod
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fmuld $nhi,$nb,$nhib
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fmuld $ahi,$bc,$ahic
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@ -345,41 +356,13 @@ $fname:
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std $nloa,[%sp+$bias+$frame+0]
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std $nlob,[%sp+$bias+$frame+8]
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addcc $j,8,$j
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std $nloc,[%sp+$bias+$frame+16]
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bz,pn %icc,.L1stskip
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std $nlod,[%sp+$bias+$frame+24]
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addcc $j,8,$j
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bz,pn %icc,.L1stskip
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.align 32,0x1000000
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.L1st:
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ldx [%sp+$bias+$frame+0],%o0
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ldx [%sp+$bias+$frame+8],%o1
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ldx [%sp+$bias+$frame+16],%o2
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ldx [%sp+$bias+$frame+24],%o3
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srlx %o0,16,%o7
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add %o7,%o1,%o1
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srlx %o1,16,%o7
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add %o7,%o2,%o2
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srlx %o2,16,%o7
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add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
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and %o0,$mask,%o0
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and %o1,$mask,%o1
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and %o2,$mask,%o2
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sllx %o1,16,%o1
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sllx %o2,32,%o2
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sllx %o3,48,%o7
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or %o1,%o0,%o0
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or %o2,%o0,%o0
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or %o7,%o0,%o0 ! 64-bit result
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addcc %g1,%o0,%o0
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srlx %o3,16,%g1 ! 34-bit carry
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bcs,a %xcc,.+8
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add %g1,1,%g1
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stx %o0,[$tp] ! tp[j-1]=
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add $ap,$j,%o4
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add $np,$j,%o5
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ld [%o4+0],$alo_ ! load a[j] as pair of 32-bit words
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@ -396,35 +379,61 @@ $fname:
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fxtod $nlo,$nlo
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fxtod $nhi,$nhi
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std $alo,[$ap_l+$j] ! save smashed ap[j] in double format
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ldx [%sp+$bias+$frame+0],%o0
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fmuld $alo,$ba,$aloa
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std $ahi,[$ap_h+$j]
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ldx [%sp+$bias+$frame+8],%o1
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fmuld $nlo,$na,$nloa
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std $nlo,[$np_l+$j] ! save smashed np[j] in double format
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ldx [%sp+$bias+$frame+16],%o2
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fmuld $alo,$bb,$alob
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std $nhi,[$np_h+$j]
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ldx [%sp+$bias+$frame+24],%o3
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fmuld $nlo,$nb,$nlob
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srlx %o0,16,%o7
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std $alo,[$ap_l+$j] ! save smashed ap[j] in double format
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fmuld $alo,$bc,$aloc
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add %o7,%o1,%o1
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std $ahi,[$ap_h+$j]
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faddd $aloa,$nloa,$nloa
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fmuld $nlo,$nc,$nloc
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srlx %o1,16,%o7
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std $nlo,[$np_l+$j] ! save smashed np[j] in double format
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fmuld $alo,$bd,$alod
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add %o7,%o2,%o2
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std $nhi,[$np_h+$j]
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faddd $alob,$nlob,$nlob
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fmuld $nlo,$nd,$nlod
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srlx %o2,16,%o7
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fmuld $ahi,$ba,$ahia
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add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
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and %o0,$mask,%o0
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faddd $aloc,$nloc,$nloc
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fmuld $nhi,$na,$nhia
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and %o1,$mask,%o1
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and %o2,$mask,%o2
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fmuld $ahi,$bb,$ahib
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sllx %o1,16,%o1
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faddd $alod,$nlod,$nlod
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fmuld $nhi,$nb,$nhib
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sllx %o2,32,%o2
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fmuld $ahi,$bc,$ahic
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sllx %o3,48,%o7
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or %o1,%o0,%o0
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faddd $ahia,$nhia,$nhia
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fmuld $nhi,$nc,$nhic
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or %o2,%o0,%o0
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fmuld $ahi,$bd,$ahid
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or %o7,%o0,%o0 ! 64-bit result
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faddd $ahib,$nhib,$nhib
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fmuld $nhi,$nd,$nhid
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addcc %g1,%o0,%o0
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faddd $dota,$nloa,$nloa
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srlx %o3,16,%g1 ! 34-bit carry
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faddd $dotb,$nlob,$nlob
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bcs,a %xcc,.+8
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add %g1,1,%g1
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stx %o0,[$tp] ! tp[j-1]=
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faddd $ahic,$nhic,$dota ! $nhic
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faddd $ahid,$nhid,$dotb ! $nhid
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@ -579,36 +588,9 @@ $fname:
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std $nloa,[%sp+$bias+$frame+0]
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std $nlob,[%sp+$bias+$frame+8]
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std $nloc,[%sp+$bias+$frame+16]
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std $nlod,[%sp+$bias+$frame+24]
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ldx [%sp+$bias+$frame+0],%o0
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ldx [%sp+$bias+$frame+8],%o1
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ldx [%sp+$bias+$frame+16],%o2
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ldx [%sp+$bias+$frame+24],%o3
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srlx %o0,16,%o7
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add %o7,%o1,%o1
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srlx %o1,16,%o7
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add %o7,%o2,%o2
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srlx %o2,16,%o7
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add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
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! why?
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and %o0,$mask,%o0
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and %o1,$mask,%o1
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and %o2,$mask,%o2
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sllx %o1,16,%o1
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sllx %o2,32,%o2
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sllx %o3,48,%o7
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or %o1,%o0,%o0
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or %o2,%o0,%o0
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or %o7,%o0,%o0 ! 64-bit result
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ldx [$tp],%o7
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addcc %o7,%o0,%o0
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! end-of-why?
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srlx %o3,16,%g1 ! 34-bit carry
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bcs,a %xcc,.+8
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add %g1,1,%g1
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add $j,8,$j
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std $nlod,[%sp+$bias+$frame+24]
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ldd [$ap_l+$j],$alo ! load a[j] in double format
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ldd [$ap_h+$j],$ahi
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ldd [$np_l+$j],$nlo ! load n[j] in double format
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@ -619,137 +601,160 @@ $fname:
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fmuld $alo,$bb,$alob
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fmuld $nlo,$nb,$nlob
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fmuld $alo,$bc,$aloc
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ldx [%sp+$bias+$frame+0],%o0
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faddd $aloa,$nloa,$nloa
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fmuld $nlo,$nc,$nloc
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ldx [%sp+$bias+$frame+8],%o1
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fmuld $alo,$bd,$alod
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ldx [%sp+$bias+$frame+16],%o2
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faddd $alob,$nlob,$nlob
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fmuld $nlo,$nd,$nlod
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ldx [%sp+$bias+$frame+24],%o3
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fmuld $ahi,$ba,$ahia
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srlx %o0,16,%o7
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faddd $aloc,$nloc,$nloc
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fmuld $nhi,$na,$nhia
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add %o7,%o1,%o1
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fmuld $ahi,$bb,$ahib
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srlx %o1,16,%o7
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faddd $alod,$nlod,$nlod
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fmuld $nhi,$nb,$nhib
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add %o7,%o2,%o2
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fmuld $ahi,$bc,$ahic
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srlx %o2,16,%o7
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faddd $ahia,$nhia,$nhia
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fmuld $nhi,$nc,$nhic
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add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
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! why?
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and %o0,$mask,%o0
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fmuld $ahi,$bd,$ahid
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and %o1,$mask,%o1
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and %o2,$mask,%o2
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faddd $ahib,$nhib,$nhib
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fmuld $nhi,$nd,$nhid
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sllx %o1,16,%o1
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faddd $dota,$nloa,$nloa
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sllx %o2,32,%o2
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faddd $dotb,$nlob,$nlob
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sllx %o3,48,%o7
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or %o1,%o0,%o0
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faddd $ahic,$nhic,$dota ! $nhic
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or %o2,%o0,%o0
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faddd $ahid,$nhid,$dotb ! $nhid
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or %o7,%o0,%o0 ! 64-bit result
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ldx [$tp],%o7
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faddd $nloc,$nhia,$nloc
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addcc %o7,%o0,%o0
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! end-of-why?
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faddd $nlod,$nhib,$nlod
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srlx %o3,16,%g1 ! 34-bit carry
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fdtox $nloa,$nloa
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bcs,a %xcc,.+8
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add %g1,1,%g1
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fdtox $nlob,$nlob
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fdtox $nloc,$nloc
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fdtox $nlod,$nlod
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std $nloa,[%sp+$bias+$frame+0]
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std $nlob,[%sp+$bias+$frame+8]
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addcc $j,8,$j
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std $nloc,[%sp+$bias+$frame+16]
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bz,pn %icc,.Linnerskip
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std $nlod,[%sp+$bias+$frame+24]
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addcc $j,8,$j
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bz,pn %icc,.Linnerskip
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.align 32,0x1000000
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.Linner:
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ldd [$ap_l+$j],$alo ! load a[j] in double format
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ldd [$ap_h+$j],$ahi
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ldd [$np_l+$j],$nlo ! load n[j] in double format
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ldd [$np_h+$j],$nhi
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fmuld $alo,$ba,$aloa
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fmuld $nlo,$na,$nloa
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fmuld $alo,$bb,$alob
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fmuld $nlo,$nb,$nlob
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fmuld $alo,$bc,$aloc
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ldx [%sp+$bias+$frame+0],%o0
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faddd $aloa,$nloa,$nloa
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fmuld $nlo,$nc,$nloc
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ldx [%sp+$bias+$frame+8],%o1
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fmuld $alo,$bd,$alod
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ldx [%sp+$bias+$frame+16],%o2
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faddd $alob,$nlob,$nlob
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fmuld $nlo,$nd,$nlod
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ldx [%sp+$bias+$frame+24],%o3
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fmuld $ahi,$ba,$ahia
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srlx %o0,16,%o7
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faddd $aloc,$nloc,$nloc
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fmuld $nhi,$na,$nhia
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add %o7,%o1,%o1
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fmuld $ahi,$bb,$ahib
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srlx %o1,16,%o7
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faddd $alod,$nlod,$nlod
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fmuld $nhi,$nb,$nhib
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add %o7,%o2,%o2
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fmuld $ahi,$bc,$ahic
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srlx %o2,16,%o7
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faddd $ahia,$nhia,$nhia
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fmuld $nhi,$nc,$nhic
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add %o7,%o3,%o3 ! %o3.%o2[0..15].%o1[0..15].%o0[0..15]
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and %o0,$mask,%o0
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fmuld $ahi,$bd,$ahid
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and %o1,$mask,%o1
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and %o2,$mask,%o2
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faddd $ahib,$nhib,$nhib
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fmuld $nhi,$nd,$nhid
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sllx %o1,16,%o1
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faddd $dota,$nloa,$nloa
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sllx %o2,32,%o2
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faddd $dotb,$nlob,$nlob
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sllx %o3,48,%o7
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or %o1,%o0,%o0
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faddd $ahic,$nhic,$dota ! $nhic
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or %o2,%o0,%o0
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faddd $ahid,$nhid,$dotb ! $nhid
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or %o7,%o0,%o0 ! 64-bit result
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faddd $nloc,$nhia,$nloc
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addcc %g1,%o0,%o0
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faddd $nlod,$nhib,$nlod
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srlx %o3,16,%g1 ! 34-bit carry
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fdtox $nloa,$nloa
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bcs,a %xcc,.+8
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add %g1,1,%g1
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ldx [$tp+8],%o7 ! tp[j]
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fdtox $nlob,$nlob
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addcc %o7,%o0,%o0
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fdtox $nloc,$nloc
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bcs,a %xcc,.+8
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add %g1,1,%g1
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|
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stx %o0,[$tp] ! tp[j-1]
|
||||
|
||||
|
||||
ldd [$ap_l+$j],$alo ! load a[j] in double format
|
||||
ldd [$ap_h+$j],$ahi
|
||||
ldd [$np_l+$j],$nlo ! load n[j] in double format
|
||||
ldd [$np_h+$j],$nhi
|
||||
|
||||
fmuld $alo,$ba,$aloa
|
||||
fmuld $nlo,$na,$nloa
|
||||
fmuld $alo,$bb,$alob
|
||||
fmuld $nlo,$nb,$nlob
|
||||
fmuld $alo,$bc,$aloc
|
||||
faddd $aloa,$nloa,$nloa
|
||||
fmuld $nlo,$nc,$nloc
|
||||
fmuld $alo,$bd,$alod
|
||||
faddd $alob,$nlob,$nlob
|
||||
fmuld $nlo,$nd,$nlod
|
||||
fmuld $ahi,$ba,$ahia
|
||||
faddd $aloc,$nloc,$nloc
|
||||
fmuld $nhi,$na,$nhia
|
||||
fmuld $ahi,$bb,$ahib
|
||||
faddd $alod,$nlod,$nlod
|
||||
fmuld $nhi,$nb,$nhib
|
||||
fmuld $ahi,$bc,$ahic
|
||||
faddd $ahia,$nhia,$nhia
|
||||
fmuld $nhi,$nc,$nhic
|
||||
fmuld $ahi,$bd,$ahid
|
||||
faddd $ahib,$nhib,$nhib
|
||||
fmuld $nhi,$nd,$nhid
|
||||
|
||||
faddd $dota,$nloa,$nloa
|
||||
faddd $dotb,$nlob,$nlob
|
||||
faddd $ahic,$nhic,$dota ! $nhic
|
||||
faddd $ahid,$nhid,$dotb ! $nhid
|
||||
|
||||
faddd $nloc,$nhia,$nloc
|
||||
faddd $nlod,$nhib,$nlod
|
||||
|
||||
fdtox $nloa,$nloa
|
||||
fdtox $nlob,$nlob
|
||||
fdtox $nloc,$nloc
|
||||
fdtox $nlod,$nlod
|
||||
|
||||
std $nloa,[%sp+$bias+$frame+0]
|
||||
std $nlob,[%sp+$bias+$frame+8]
|
||||
std $nloc,[%sp+$bias+$frame+16]
|
||||
std $nlod,[%sp+$bias+$frame+24]
|
||||
|
||||
addcc $j,8,$j
|
||||
std $nlod,[%sp+$bias+$frame+24]
|
||||
bnz,pt %icc,.Linner
|
||||
add $tp,8,$tp
|
||||
|
||||
.Linnerskip:
|
||||
fdtox $dota,$dota
|
||||
fdtox $dotb,$dotb
|
||||
|
||||
ldx [%sp+$bias+$frame+0],%o0
|
||||
ldx [%sp+$bias+$frame+8],%o1
|
||||
ldx [%sp+$bias+$frame+16],%o2
|
||||
ldx [%sp+$bias+$frame+24],%o3
|
||||
|
||||
srlx %o0,16,%o7
|
||||
std $dota,[%sp+$bias+$frame+32]
|
||||
add %o7,%o1,%o1
|
||||
std $dotb,[%sp+$bias+$frame+40]
|
||||
srlx %o1,16,%o7
|
||||
add %o7,%o2,%o2
|
||||
srlx %o2,16,%o7
|
||||
@ -762,39 +767,34 @@ $fname:
|
||||
sllx %o3,48,%o7
|
||||
or %o1,%o0,%o0
|
||||
or %o2,%o0,%o0
|
||||
ldx [%sp+$bias+$frame+32],%o4
|
||||
or %o7,%o0,%o0 ! 64-bit result
|
||||
ldx [%sp+$bias+$frame+40],%o5
|
||||
addcc %g1,%o0,%o0
|
||||
ldx [$tp+8],%o7 ! tp[j]
|
||||
srlx %o3,16,%g1 ! 34-bit carry
|
||||
bcs,a %xcc,.+8
|
||||
add %g1,1,%g1
|
||||
|
||||
ldx [$tp+8],%o7 ! tp[j]
|
||||
addcc %o7,%o0,%o0
|
||||
bcs,a %xcc,.+8
|
||||
add %g1,1,%g1
|
||||
|
||||
stx %o0,[$tp] ! tp[j-1]
|
||||
add $tp,8,$tp
|
||||
|
||||
fdtox $dota,$dota
|
||||
fdtox $dotb,$dotb
|
||||
std $dota,[%sp+$bias+$frame+32]
|
||||
std $dotb,[%sp+$bias+$frame+40]
|
||||
ldx [%sp+$bias+$frame+32],%o0
|
||||
ldx [%sp+$bias+$frame+40],%o1
|
||||
|
||||
srlx %o0,16,%o7
|
||||
add %o7,%o1,%o1
|
||||
and %o0,$mask,%o0
|
||||
sllx %o1,16,%o7
|
||||
or %o7,%o0,%o0
|
||||
addcc %g1,%o0,%o0
|
||||
srlx %o1,48,%g1
|
||||
srlx %o4,16,%o7
|
||||
add %o7,%o5,%o5
|
||||
and %o4,$mask,%o4
|
||||
sllx %o5,16,%o7
|
||||
or %o7,%o4,%o4
|
||||
addcc %g1,%o4,%o4
|
||||
srlx %o5,48,%g1
|
||||
bcs,a %xcc,.+8
|
||||
add %g1,1,%g1
|
||||
|
||||
addcc $carry,%o0,%o0
|
||||
stx %o0,[$tp] ! tp[num-1]
|
||||
addcc $carry,%o4,%o4
|
||||
stx %o4,[$tp] ! tp[num-1]
|
||||
mov %g1,$carry
|
||||
bcs,a %xcc,.+8
|
||||
add $carry,1,$carry
|
||||
|
Loading…
Reference in New Issue
Block a user