x86_64cpuid.pl: get AVX masking right.
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@ -146,12 +146,10 @@ OPENSSL_ia32_cpuid:
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.Lgeneric:
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.Lgeneric:
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and \$0x00000800,%r9d # isolate AMD XOP flag
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and \$0x00000800,%r9d # isolate AMD XOP flag
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and \$0xfffff7ff,%ecx
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and \$0xfffff7ff,%ecx
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or %r9d,%ecx # merge AMD XOP flag
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or %ecx,%r9d # merge AMD XOP flag
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shl \$32,%rcx
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mov %edx,%r10d # %r9d:%r10d is copy of %ecx:%edx
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mov %edx,%ebx
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bt \$27,%r9d # check OSXSAVE bit
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or %rcx,%rbx # compose capability vector in %rbx
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bt \$27+32,%rcx # check OSXSAVE bit
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jnc .Lclear_avx
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jnc .Lclear_avx
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xor %ecx,%ecx # XCR0
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xor %ecx,%ecx # XCR0
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.byte 0x0f,0x01,0xd0 # xgetbv
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.byte 0x0f,0x01,0xd0 # xgetbv
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@ -160,11 +158,12 @@ OPENSSL_ia32_cpuid:
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je .Ldone
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je .Ldone
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.Lclear_avx:
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.Lclear_avx:
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mov \$0xefffe7ff,%eax # ~(1<<28|1<<12|1<<11)
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mov \$0xefffe7ff,%eax # ~(1<<28|1<<12|1<<11)
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shl \$32,%rax
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and %eax,%r9d # clear AVX, FMA and AMD XOP bits
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and %rax,%rbx # clear AVX, FMA and AMD XOP bits
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.Ldone:
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.Ldone:
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mov %rbx,%rax
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shl \$32,%r9
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mov %r10d,%eax
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mov %r8,%rbx # restore %rbx
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mov %r8,%rbx # restore %rbx
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or %r9,%rax
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ret
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ret
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.size OPENSSL_ia32_cpuid,.-OPENSSL_ia32_cpuid
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.size OPENSSL_ia32_cpuid,.-OPENSSL_ia32_cpuid
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