ghash-sparcv9.pl: add VIS3 code path.
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@ -36,6 +36,13 @@
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# references to input data and Z.hi updates to achieve 12 cycles
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# timing. To anchor to something else, sha1-sparcv9.pl spends 11.6
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# cycles to process one byte on UltraSPARC pre-Tx CPU and ~24 on T1.
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#
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# October 2012
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#
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# Add VIS3 lookup-table-free implementation using polynomial
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# multiplication xmulx[hi] and extended addition addxc[cc]
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# instructions. 3.96/6.26x improvement on T3/T4 or in absolute
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# terms 9.02/2.61 cycles per byte.
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$bits=32;
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for (@ARGV) { $bits=64 if (/\-m64/ || /\-xarch\=v9/); }
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@ -66,6 +73,10 @@ $Htbl="%i1";
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$inp="%i2";
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$len="%i3";
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$code.=<<___ if ($bits==64);
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.register %g2,#scratch
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.register %g3,#scratch
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___
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$code.=<<___;
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.section ".text",#alloc,#execinstr
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@ -321,10 +332,213 @@ gcm_gmult_4bit:
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restore
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.type gcm_gmult_4bit,#function
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.size gcm_gmult_4bit,(.-gcm_gmult_4bit)
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.asciz "GHASH for SPARCv9, CRYPTOGAMS by <appro\@openssl.org>"
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___
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{{{
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# Straightforward 64-bits-at-a-time approach with pair of 128x64-bit
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# multiplications followed by 64-bit reductions. While it might be
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# suboptimal with regard to sheer amount of multiplications, other
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# methods would require larger amount of 64-bit registers, which we
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# don't have in 32-bit application. Also, they [alternative methods
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# such as aggregated reduction] kind of thrive on fast 128-bit SIMD
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# instructions and these are not option on SPARC...
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($Xip,$Htable,$inp,$len)=map("%i$_",(0..3));
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($xE1,$Hhi,$Hlo,$Rhi,$Rlo,$M0hi,$M0lo,$M1hi,$M1lo,$Zhi,$Zlo,$X)=
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(map("%g$_",(1..5)),map("%o$_",(0..5,7)));
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($shl,$shr)=map("%l$_",(0..7));
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$code.=<<___;
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.globl gcm_gmult_vis3
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.align 32
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gcm_gmult_vis3:
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save %sp,-$frame,%sp
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ldx [$Xip+8],$X ! load X.lo
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ldx [$Htable-8], $Hlo ! load H
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ldx [$Htable-16],$Hhi
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mov 0xE1,$xE1
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sllx $xE1,57,$xE1
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xmulx $X,$Hlo,$M0lo ! H·X.lo
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xmulxhi $X,$Hlo,$M0hi
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xmulx $X,$Hhi,$M1lo
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xmulxhi $X,$Hhi,$M1hi
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ldx [$Xip+0],$X ! load X.hi
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addcc $M0lo,$M0lo,$M0lo ! (H·X.lo)<<1
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xor $M0hi,$M1lo,$M1lo
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xmulx $xE1,$M0lo,$Rlo ! res=Z.lo·(0xE1<<57)
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xmulxhi $xE1,$M0lo,$Rhi
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addxccc $M1lo,$M1lo,$Zlo ! Z=((H·X.lo)<<1)>>64
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addxc $M1hi,$M1hi,$Zhi
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xor $M0lo,$Zhi,$Zhi ! overflow bit from 0xE1<<57
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xmulx $X,$Hlo,$M0lo ! H·X.hi
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xmulxhi $X,$Hlo,$M0hi
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xmulx $X,$Hhi,$M1lo
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xmulxhi $X,$Hhi,$M1hi
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xor $Rlo,$Zlo,$Zlo ! Z^=res
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xor $Rhi,$Zhi,$Zhi
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addcc $M0lo,$M0lo,$M0lo ! (H·X.lo)<<1
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xor $Zlo, $M0lo,$M0lo
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xor $M0hi,$M1lo,$M1lo
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xmulx $xE1,$M0lo,$Rlo ! res=Z.lo·(0xE1<<57)
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xmulxhi $xE1,$M0lo,$Rhi
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addxccc $M1lo,$M1lo,$M1lo
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addxc $M1hi,$M1hi,$M1hi
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xor $M1lo,$Zhi,$Zlo ! Z=(Z^(H·X.hi)<<1)>>64
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xor $M0lo,$M1hi,$Zhi ! overflow bit from 0xE1<<57
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xor $Rlo,$Zlo,$Zlo ! Z^=res
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xor $Rhi,$Zhi,$Zhi
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stx $Zlo,[$Xip+8] ! save Xi
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stx $Zhi,[$Xip+0]
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ret
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restore
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.type gcm_gmult_vis3,#function
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.size gcm_gmult_vis3,.-gcm_gmult_vis3
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.globl gcm_ghash_vis3
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.align 32
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gcm_ghash_vis3:
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save %sp,-$frame,%sp
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ldx [$Xip+0],$Zhi ! load X.hi
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ldx [$Xip+8],$Zlo ! load X.lo
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and $inp,7,$shl
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andn $inp,7,$inp
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ldx [$Htable-8], $Hlo ! load H
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ldx [$Htable-16],$Hhi
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sll $shl,3,$shl
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prefetch [$inp+63], 20
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mov 0xE1,$xE1
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sub %g0,$shl,$shr
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sllx $xE1,57,$xE1
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.Loop:
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ldx [$inp+8],$Rlo ! load *inp
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brz,pt $shl,1f
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ldx [$inp+0],$Rhi
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ldx [$inp+16],$X ! align data
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srlx $Rlo,$shr,$M0lo
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sllx $Rlo,$shl,$Rlo
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sllx $Rhi,$shl,$Rhi
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srlx $X,$shr,$X
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or $M0lo,$Rhi,$Rhi
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or $X,$Rlo,$Rlo
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1:
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add $inp,16,$inp
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sub $len,16,$len
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xor $Rlo,$Zlo,$X
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prefetch [$inp+63], 20
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xmulx $X,$Hlo,$M0lo ! H·X.lo
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xmulxhi $X,$Hlo,$M0hi
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xmulx $X,$Hhi,$M1lo
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xmulxhi $X,$Hhi,$M1hi
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xor $Rhi,$Zhi,$X
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addcc $M0lo,$M0lo,$M0lo ! (H·X.lo)<<1
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xor $M0hi,$M1lo,$M1lo
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xmulx $xE1,$M0lo,$Rlo ! res=Z.lo·(0xE1<<57)
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xmulxhi $xE1,$M0lo,$Rhi
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addxccc $M1lo,$M1lo,$Zlo ! Z=((H·X.lo)<<1)>>64
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addxc $M1hi,$M1hi,$Zhi
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xor $M0lo,$Zhi,$Zhi ! overflow bit from 0xE1<<57
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xmulx $X,$Hlo,$M0lo ! H·X.hi
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xmulxhi $X,$Hlo,$M0hi
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xmulx $X,$Hhi,$M1lo
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xmulxhi $X,$Hhi,$M1hi
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xor $Rlo,$Zlo,$Zlo ! Z^=res
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xor $Rhi,$Zhi,$Zhi
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addcc $M0lo,$M0lo,$M0lo ! (H·X.lo)<<1
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xor $Zlo, $M0lo,$M0lo
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xor $M0hi,$M1lo,$M1lo
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xmulx $xE1,$M0lo,$Rlo ! res=Z.lo·(0xE1<<57)
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xmulxhi $xE1,$M0lo,$Rhi
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addxccc $M1lo,$M1lo,$M1lo
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addxc $M1hi,$M1hi,$M1hi
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xor $M1lo,$Zhi,$Zlo ! Z=(Z^(H·X.hi)<<1)>>64
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xor $M0lo,$M1hi,$Zhi ! overflow bit from 0xE1<<57
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xor $Rlo,$Zlo,$Zlo ! Z^=res
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brnz,pt $len,.Loop
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xor $Rhi,$Zhi,$Zhi
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stx $Zlo,[$Xip+8] ! save Xi
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stx $Zhi,[$Xip+0]
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ret
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restore
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.type gcm_ghash_vis3,#function
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.size gcm_ghash_vis3,.-gcm_ghash_vis3
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___
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}}}
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$code.=<<___;
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.asciz "GHASH for SPARCv9/VIS3, CRYPTOGAMS by <appro\@openssl.org>"
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.align 4
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___
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$code =~ s/\`([^\`]*)\`/eval $1/gem;
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print $code;
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# Purpose of these subroutines is to explicitly encode VIS instructions,
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# so that one can compile the module without having to specify VIS
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# extentions on compiler command line, e.g. -xarch=v9 vs. -xarch=v9a.
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# Idea is to reserve for option to produce "universal" binary and let
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# programmer detect if current CPU is VIS capable at run-time.
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sub unvis3 {
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my ($mnemonic,$rs1,$rs2,$rd)=@_;
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my %bias = ( "g" => 0, "o" => 8, "l" => 16, "i" => 24 );
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my ($ref,$opf);
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my %visopf = ( "addxc" => 0x011,
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"addxccc" => 0x013,
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"xmulx" => 0x115,
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"xmulxhi" => 0x116 );
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$ref = "$mnemonic\t$rs1,$rs2,$rd";
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if ($opf=$visopf{$mnemonic}) {
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foreach ($rs1,$rs2,$rd) {
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return $ref if (!/%([goli])([0-9])/);
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$_=$bias{$1}+$2;
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}
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return sprintf ".word\t0x%08x !%s",
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0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
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$ref;
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} else {
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return $ref;
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}
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}
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foreach (split("\n",$code)) {
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s/\`([^\`]*)\`/eval $1/ge;
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s/\b(xmulx[hi]*|addxc[c]{0,2})\s+(%[goli][0-7]),\s*(%[goli][0-7]),\s*(%[goli][0-7])/
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&unvis3($1,$2,$3,$4)
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/ge;
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print $_,"\n";
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}
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close STDOUT;
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@ -674,6 +674,13 @@ void gcm_ghash_4bit_x86(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len
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void gcm_gmult_neon(u64 Xi[2],const u128 Htable[16]);
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void gcm_ghash_neon(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);
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# endif
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# elif defined(__sparc__) || defined(__sparc)
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# include "sparc_arch.h"
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# define GHASH_ASM_SPARC
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# define GCM_FUNCREF_4BIT
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extern unsigned int OPENSSL_sparcv9cap_P[];
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void gcm_gmult_vis3(u64 Xi[2],const u128 Htable[16]);
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void gcm_ghash_vis3(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);
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# endif
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#endif
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@ -750,6 +757,15 @@ void CRYPTO_gcm128_init(GCM128_CONTEXT *ctx,void *key,block128_f block)
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ctx->gmult = gcm_gmult_4bit;
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ctx->ghash = gcm_ghash_4bit;
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}
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# elif defined(GHASH_ASM_SPARC)
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if (OPENSSL_sparcv9cap_P[0] & SPARCV9_VIS3) {
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ctx->gmult = gcm_gmult_vis3;
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ctx->ghash = gcm_ghash_vis3;
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} else {
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gcm_init_4bit(ctx->Htable,ctx->H.u);
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ctx->gmult = gcm_gmult_4bit;
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ctx->ghash = gcm_ghash_4bit;
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}
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# else
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gcm_init_4bit(ctx->Htable,ctx->H.u);
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# endif
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