x86[_64]cpuid.pl: harmonize OPENSSL_ia32_cpuid [from HEAD].
This commit is contained in:
Andy Polyakov
parent
4a46dc6e5c
commit
10fd0b7b55
@ -7,15 +7,24 @@ if ($flavour =~ /\./) { $output = $flavour; undef $flavour; }
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$win64=0; $win64=1 if ($flavour =~ /[nm]asm|mingw64/ || $output =~ /\.asm$/);
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$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
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open STDOUT,"| $^X ${dir}perlasm/x86_64-xlate.pl $flavour $output";
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( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or
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( $xlate="${dir}perlasm/x86_64-xlate.pl" and -f $xlate) or
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die "can't locate x86_64-xlate.pl";
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open STDOUT,"| $^X $xlate $flavour $output";
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($arg1,$arg2,$arg3,$arg4)=$win64?("%rcx","%rdx","%r8", "%r9") : # Win64 order
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("%rdi","%rsi","%rdx","%rcx"); # Unix order
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if ($win64) { $arg1="%rcx"; $arg2="%rdx"; }
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else { $arg1="%rdi"; $arg2="%rsi"; }
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print<<___;
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.extern OPENSSL_cpuid_setup
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.hidden OPENSSL_cpuid_setup
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.section .init
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call OPENSSL_cpuid_setup
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.hidden OPENSSL_ia32cap_P
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.comm OPENSSL_ia32cap_P,8
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.text
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.globl OPENSSL_atomic_add
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@ -46,7 +55,7 @@ OPENSSL_rdtsc:
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.type OPENSSL_ia32_cpuid,\@abi-omnipotent
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.align 16
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OPENSSL_ia32_cpuid:
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mov %rbx,%r8
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mov %rbx,%r8 # save %rbx
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xor %eax,%eax
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cpuid
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@ -78,7 +87,15 @@ OPENSSL_ia32_cpuid:
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# AMD specific
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mov \$0x80000000,%eax
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cpuid
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cmp \$0x80000008,%eax
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cmp \$0x80000001,%eax
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jb .Lintel
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mov %eax,%r10d
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mov \$0x80000001,%eax
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cpuid
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or %ecx,%r9d
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and \$0x00000801,%r9d # isolate AMD XOP bit, 1<<11
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cmp \$0x80000008,%r10d
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jb .Lintel
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mov \$0x80000008,%eax
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@ -89,12 +106,12 @@ OPENSSL_ia32_cpuid:
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mov \$1,%eax
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cpuid
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bt \$28,%edx # test hyper-threading bit
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jnc .Ldone
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jnc .Lgeneric
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shr \$16,%ebx # number of logical processors
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cmp %r10b,%bl
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ja .Ldone
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ja .Lgeneric
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and \$0xefffffff,%edx # ~(1<<28)
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jmp .Ldone
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jmp .Lgeneric
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.Lintel:
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cmp \$4,%r11d
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@ -111,30 +128,47 @@ OPENSSL_ia32_cpuid:
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.Lnocacheinfo:
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mov \$1,%eax
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cpuid
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and \$0xbfefffff,%edx # force reserved bits to 0
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cmp \$0,%r9d
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jne .Lnotintel
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or \$0x00100000,%edx # use reserved 20th bit to engage RC4_CHAR
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or \$0x40000000,%edx # set reserved bit#30 on Intel CPUs
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and \$15,%ah
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cmp \$15,%ah # examine Family ID
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je .Lnotintel
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or \$0x40000000,%edx # use reserved bit to skip unrolled loop
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jne .Lnotintel
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or \$0x00100000,%edx # set reserved bit#20 to engage RC4_CHAR
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.Lnotintel:
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bt \$28,%edx # test hyper-threading bit
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jnc .Ldone
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jnc .Lgeneric
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and \$0xefffffff,%edx # ~(1<<28)
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cmp \$0,%r10d
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je .Ldone
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je .Lgeneric
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or \$0x10000000,%edx # 1<<28
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shr \$16,%ebx
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cmp \$1,%bl # see if cache is shared
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ja .Ldone
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ja .Lgeneric
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and \$0xefffffff,%edx # ~(1<<28)
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.Lgeneric:
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and \$0x00000800,%r9d # isolate AMD XOP flag
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and \$0xfffff7ff,%ecx
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or %ecx,%r9d # merge AMD XOP flag
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mov %edx,%r10d # %r9d:%r10d is copy of %ecx:%edx
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bt \$27,%r9d # check OSXSAVE bit
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jnc .Lclear_avx
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xor %ecx,%ecx # XCR0
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.byte 0x0f,0x01,0xd0 # xgetbv
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and \$6,%eax # isolate XMM and YMM state support
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cmp \$6,%eax
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je .Ldone
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.Lclear_avx:
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mov \$0xefffe7ff,%eax # ~(1<<28|1<<12|1<<11)
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and %eax,%r9d # clear AVX, FMA and AMD XOP bits
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.Ldone:
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shl \$32,%rcx
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mov %edx,%eax
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mov %r8,%rbx
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or %rcx,%rax
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shl \$32,%r9
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mov %r10d,%eax
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mov %r8,%rbx # restore %rbx
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or %r9,%rax
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ret
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.size OPENSSL_ia32_cpuid,.-OPENSSL_ia32_cpuid
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@ -20,7 +20,7 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
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&pop ("eax");
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&xor ("ecx","eax");
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&bt ("ecx",21);
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&jnc (&label("done"));
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&jnc (&label("generic"));
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&xor ("eax","eax");
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&cpuid ();
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&mov ("edi","eax"); # max value for standard query level
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@ -51,7 +51,14 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
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# AMD specific
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&mov ("eax",0x80000000);
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&cpuid ();
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&cmp ("eax",0x80000008);
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&cmp ("eax",0x80000001);
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&jb (&label("intel"));
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&mov ("esi","eax");
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&mov ("eax",0x80000001);
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&cpuid ();
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&or ("ebp","ecx");
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&and ("ebp",1<<11|1); # isolate XOP bit
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&cmp ("esi",0x80000008);
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&jb (&label("intel"));
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&mov ("eax",0x80000008);
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@ -62,13 +69,13 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
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&mov ("eax",1);
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&cpuid ();
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&bt ("edx",28);
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&jnc (&label("done"));
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&jnc (&label("generic"));
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&shr ("ebx",16);
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&and ("ebx",0xff);
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&cmp ("ebx","esi");
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&ja (&label("done"));
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&ja (&label("generic"));
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&and ("edx",0xefffffff); # clear hyper-threading bit
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&jmp (&label("done"));
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&jmp (&label("generic"));
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&set_label("intel");
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&cmp ("edi",4);
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@ -85,27 +92,52 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
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&set_label("nocacheinfo");
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&mov ("eax",1);
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&cpuid ();
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&and ("edx",0xbfefffff); # force reserved bits #20, #30 to 0
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&cmp ("ebp",0);
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&jne (&label("notP4"));
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&jne (&label("notintel"));
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&or ("edx",1<<30); # set reserved bit#30 on Intel CPUs
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&and (&HB("eax"),15); # familiy ID
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&cmp (&HB("eax"),15); # P4?
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&jne (&label("notP4"));
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&or ("edx",1<<20); # use reserved bit to engage RC4_CHAR
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&set_label("notP4");
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&jne (&label("notintel"));
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&or ("edx",1<<20); # set reserved bit#20 to engage RC4_CHAR
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&set_label("notintel");
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&bt ("edx",28); # test hyper-threading bit
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&jnc (&label("done"));
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&jnc (&label("generic"));
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&and ("edx",0xefffffff);
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&cmp ("edi",0);
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&je (&label("done"));
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&je (&label("generic"));
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&or ("edx",0x10000000);
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&shr ("ebx",16);
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&cmp (&LB("ebx"),1);
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&ja (&label("done"));
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&ja (&label("generic"));
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&and ("edx",0xefffffff); # clear hyper-threading bit if not
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&set_label("generic");
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&and ("ebp",1<<11); # isolate AMD XOP flag
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&and ("ecx",0xfffff7ff); # force 11th bit to 0
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&mov ("esi","edx");
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&or ("ebp","ecx"); # merge AMD XOP flag
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&bt ("ecx",26); # check XSAVE bit
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&jnc (&label("done"));
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&bt ("ecx",27); # check OSXSAVE bit
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&jnc (&label("clear_xmm"));
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&xor ("ecx","ecx");
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&data_byte(0x0f,0x01,0xd0); # xgetbv
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&and ("eax",6);
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&cmp ("eax",6);
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&je (&label("done"));
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&cmp ("eax",2);
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&je (&label("clear_avx"));
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&set_label("clear_xmm");
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&and ("ebp",0xfdfffffd); # clear AESNI and PCLMULQDQ bits
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&and ("esi",0xfeffffff); # clear FXSR
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&set_label("clear_avx");
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&and ("ebp",0xefffe7ff); # clear AVX, FMA and AMD XOP bits
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&set_label("done");
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&mov ("eax","edx");
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&mov ("edx","ecx");
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&mov ("eax","esi");
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&mov ("edx","ebp");
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&function_end("OPENSSL_ia32_cpuid");
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&external_label("OPENSSL_ia32cap_P");
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@ -199,8 +231,9 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); }
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&bt (&DWP(0,"ecx"),1);
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&jnc (&label("no_x87"));
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if ($sse2) {
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&bt (&DWP(0,"ecx"),26);
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&jnc (&label("no_sse2"));
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&and ("ecx",1<<26|1<<24); # check SSE2 and FXSR bits
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&cmp ("ecx",1<<26|1<<24);
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&jne (&label("no_sse2"));
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&pxor ("xmm0","xmm0");
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&pxor ("xmm1","xmm1");
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&pxor ("xmm2","xmm2");
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