MIPS assembly pack: get rid of deprecated instructions.
Latest MIPS ISA specification declared 'branch likely' instructions obsolete. To makes code future-proof replace them with equivalent.
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@ -133,7 +133,7 @@ $code.=<<___;
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bnez $at,1f
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li $t0,0
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slt $at,$num,17 # on in-order CPU
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bnezl $at,bn_mul_mont_internal
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bnez $at,bn_mul_mont_internal
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nop
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1: jr $ra
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li $a0,0
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@ -140,10 +140,10 @@ $code.=<<___;
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.set reorder
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li $minus4,-4
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and $ta0,$a2,$minus4
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$LD $t0,0($a1)
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beqz $ta0,.L_bn_mul_add_words_tail
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.L_bn_mul_add_words_loop:
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$LD $t0,0($a1)
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$MULTU $t0,$a3
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$LD $t1,0($a0)
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$LD $t2,$BNSZ($a1)
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@ -200,10 +200,9 @@ $code.=<<___;
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$ADDU $v0,$ta2
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sltu $at,$ta3,$at
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$ST $ta3,-$BNSZ($a0)
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$ADDU $v0,$at
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.set noreorder
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bgtzl $ta0,.L_bn_mul_add_words_loop
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$LD $t0,0($a1)
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bgtz $ta0,.L_bn_mul_add_words_loop
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$ADDU $v0,$at
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beqz $a2,.L_bn_mul_add_words_return
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nop
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@ -300,10 +299,10 @@ $code.=<<___;
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.set reorder
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li $minus4,-4
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and $ta0,$a2,$minus4
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$LD $t0,0($a1)
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beqz $ta0,.L_bn_mul_words_tail
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.L_bn_mul_words_loop:
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$LD $t0,0($a1)
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$MULTU $t0,$a3
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$LD $t2,$BNSZ($a1)
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$LD $ta0,2*$BNSZ($a1)
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@ -341,10 +340,9 @@ $code.=<<___;
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$ADDU $v0,$at
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sltu $ta3,$v0,$at
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$ST $v0,-$BNSZ($a0)
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$ADDU $v0,$ta3,$ta2
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.set noreorder
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bgtzl $ta0,.L_bn_mul_words_loop
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$LD $t0,0($a1)
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bgtz $ta0,.L_bn_mul_words_loop
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$ADDU $v0,$ta3,$ta2
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beqz $a2,.L_bn_mul_words_return
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nop
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@ -429,10 +427,10 @@ $code.=<<___;
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.set reorder
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li $minus4,-4
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and $ta0,$a2,$minus4
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$LD $t0,0($a1)
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beqz $ta0,.L_bn_sqr_words_tail
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.L_bn_sqr_words_loop:
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$LD $t0,0($a1)
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$MULTU $t0,$t0
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$LD $t2,$BNSZ($a1)
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$LD $ta0,2*$BNSZ($a1)
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@ -463,11 +461,10 @@ $code.=<<___;
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mflo $ta3
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mfhi $ta2
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$ST $ta3,-2*$BNSZ($a0)
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$ST $ta2,-$BNSZ($a0)
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.set noreorder
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bgtzl $ta0,.L_bn_sqr_words_loop
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$LD $t0,0($a1)
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bgtz $ta0,.L_bn_sqr_words_loop
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$ST $ta2,-$BNSZ($a0)
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beqz $a2,.L_bn_sqr_words_return
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nop
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@ -547,10 +544,10 @@ $code.=<<___;
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.set reorder
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li $minus4,-4
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and $at,$a3,$minus4
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$LD $t0,0($a1)
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beqz $at,.L_bn_add_words_tail
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.L_bn_add_words_loop:
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$LD $t0,0($a1)
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$LD $ta0,0($a2)
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subu $a3,4
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$LD $t1,$BNSZ($a1)
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@ -589,11 +586,10 @@ $code.=<<___;
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$ADDU $t3,$ta3,$v0
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sltu $v0,$t3,$ta3
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$ST $t3,-$BNSZ($a0)
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$ADDU $v0,$t9
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.set noreorder
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bgtzl $at,.L_bn_add_words_loop
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$LD $t0,0($a1)
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bgtz $at,.L_bn_add_words_loop
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$ADDU $v0,$t9
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beqz $a3,.L_bn_add_words_return
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nop
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@ -679,10 +675,10 @@ $code.=<<___;
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.set reorder
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li $minus4,-4
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and $at,$a3,$minus4
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$LD $t0,0($a1)
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beqz $at,.L_bn_sub_words_tail
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.L_bn_sub_words_loop:
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$LD $t0,0($a1)
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$LD $ta0,0($a2)
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subu $a3,4
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$LD $t1,$BNSZ($a1)
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@ -722,11 +718,10 @@ $code.=<<___;
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$SUBU $t3,$ta3,$v0
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sgtu $v0,$t3,$ta3
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$ST $t3,-$BNSZ($a0)
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$ADDU $v0,$t9
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.set noreorder
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bgtzl $at,.L_bn_sub_words_loop
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$LD $t0,0($a1)
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bgtz $at,.L_bn_sub_words_loop
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$ADDU $v0,$t9
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beqz $a3,.L_bn_sub_words_return
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nop
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@ -840,8 +835,9 @@ $code.=<<___;
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sltu $ta0,$a1,$a2
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or $t8,$ta0
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.set noreorder
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beqzl $at,.L_bn_div_3_words_inner_loop
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beqz $at,.L_bn_div_3_words_inner_loop
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$SUBU $v0,1
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$ADDU $v0,1
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.set reorder
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.L_bn_div_3_words_inner_loop_done:
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.set noreorder
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@ -902,7 +898,8 @@ $code.=<<___;
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and $t2,$a0
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$SRL $at,$a1,$t1
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.set noreorder
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bnezl $t2,.+8
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beqz $t2,.+12
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nop
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break 6 # signal overflow
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.set reorder
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$SLL $a0,$t9
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@ -917,7 +914,8 @@ $code.=<<___;
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$SRL $DH,$a2,4*$BNSZ # bits
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sgeu $at,$a0,$a2
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.set noreorder
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bnezl $at,.+8
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beqz $at,.+12
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nop
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$SUBU $a0,$a2
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.set reorder
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@ -406,7 +406,7 @@ $code.=<<___;
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$ST $G,6*$SZ($ctx)
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$ST $H,7*$SZ($ctx)
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bnel $inp,@X[15],.Loop
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bne $inp,@X[15],.Loop
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$PTR_SUB $Ktbl,`($rounds-16)*$SZ` # rewind $Ktbl
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$REG_L $ra,$FRAMESIZE-1*$SZREG($sp)
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