f38111d76b
Squashed commit of the following: commit 26be4c66686d2d75ba1eb381ae562d30474429b2 Merge: 91bde828df0566Author: Licai Guo <guolicai@gmail.com> Date: Wed Jan 8 16:56:49 2014 -0800 Merge remote-tracking branch 'upstream/master' into move_to_common Conflicts: codec/common/targets.mk codec/console/dec/targets.mk codec/decoder/targets.mk codec/encoder/targets.mk codec/processing/targets.mk commit 91bde8209dad40eaa0b26cc75467e4ce52b4c8ae Merge: c827054cc2ffeeAuthor: Licai Guo <guolicai@gmail.com> Date: Tue Jan 7 20:16:11 2014 -0800 Merge remote-tracking branch 'upstream/master' into move_to_common commit c8270543fab8e40cb4aebf62d7646068afe19484 Author: Licai Guo <guolicai@gmail.com> Date: Mon Jan 6 19:12:39 2014 -0800 enable WelsScan4x4DcAc_ssse3 commit c8d2823d54e54cab146098302441ef44a4638382 Author: Licai Guo <guolicai@gmail.com> Date: Mon Jan 6 18:46:06 2014 -0800 remove trailing white spaces commit 39866a9cf54db6120aabd6a01afd4aedbead8af0 Author: Licai Guo <guolicai@gmail.com> Date: Mon Jan 6 18:06:10 2014 -0800 move common code(deblocking and cpu) to common, rename decoder's Intra-prediction functions prefix.
81 lines
3.5 KiB
C
81 lines
3.5 KiB
C
/*!
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* \copy
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* Copyright (c) 2009-2013, Cisco Systems
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*
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* \file cpu_core.h
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*
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* \brief cpu core feature detection
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*
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* \date 4/24/2009 Created
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*
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*************************************************************************************
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*/
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#if !defined(WELS_CPU_CORE_FEATURE_DETECTION_H__)
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#define WELS_CPU_CORE_FEATURE_DETECTION_H__
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/*
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* WELS CPU feature flags
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*/
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#define WELS_CPU_MMX 0x00000001 /* mmx */
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#define WELS_CPU_MMXEXT 0x00000002 /* mmx-ext*/
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#define WELS_CPU_SSE 0x00000004 /* sse */
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#define WELS_CPU_SSE2 0x00000008 /* sse 2 */
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#define WELS_CPU_SSE3 0x00000010 /* sse 3 */
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#define WELS_CPU_SSE41 0x00000020 /* sse 4.1 */
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#define WELS_CPU_3DNOW 0x00000040 /* 3dnow! */
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#define WELS_CPU_3DNOWEXT 0x00000080 /* 3dnow! ext */
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#define WELS_CPU_ALTIVEC 0x00000100 /* altivec */
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#define WELS_CPU_SSSE3 0x00000200 /* ssse3 */
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#define WELS_CPU_SSE42 0x00000400 /* sse 4.2 */
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/* CPU features application extensive */
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#define WELS_CPU_AVX 0x00000800 /* Advanced Vector eXtentions */
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#define WELS_CPU_FPU 0x00001000 /* x87-FPU on chip */
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#define WELS_CPU_HTT 0x00002000 /* Hyper-Threading Technology (HTT), Multi-threading enabled feature:
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physical processor package is capable of supporting more than one logic processor
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*/
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#define WELS_CPU_CMOV 0x00004000 /* Conditional Move Instructions,
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also if x87-FPU is present at indicated by the CPUID.FPU feature bit, then FCOMI and FCMOV are supported
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*/
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#define WELS_CPU_MOVBE 0x00008000 /* MOVBE instruction */
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#define WELS_CPU_AES 0x00010000 /* AES instruction extensions */
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#define WELS_CPU_FMA 0x00020000 /* AVX VEX FMA instruction sets */
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#define WELS_CPU_CACHELINE_16 0x10000000 /* CacheLine Size 16 */
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#define WELS_CPU_CACHELINE_32 0x20000000 /* CacheLine Size 32 */
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#define WELS_CPU_CACHELINE_64 0x40000000 /* CacheLine Size 64 */
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#define WELS_CPU_CACHELINE_128 0x80000000 /* CacheLine Size 128 */
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/*
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* Interfaces for CPU core feature detection as below
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*/
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#endif//WELS_CPU_CORE_FEATURE_DETECTION_H__
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