b6c4a5447c
At lower bitrates, it is overall faster to conditionally do one block at a time with SSE2 on Haswell and likely other common architectures. At higher bitrates, it is faster to use the wider routine that IDCTs four blocks at a time. To avoid potential performance regressions as compared to MMX, stick with single-block IDCTs with SSE2. There is still a performance advantage as compared to MMX because the single-block SSE2 routine is faster than the corresponding MMX routine. Stick with four blocks at a time with AVX2 for which that appears to be consistently faster on Haswell.
199 lines
6.3 KiB
C++
199 lines
6.3 KiB
C++
#include <gtest/gtest.h>
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#include "macros.h"
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#include "decode_mb_aux.h"
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#include "deblocking.h"
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#include "cpu.h"
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using namespace WelsDec;
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namespace {
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void IdctResAddPred_ref (uint8_t* pPred, const int32_t kiStride, int16_t* pRs) {
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int16_t iSrc[16];
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uint8_t* pDst = pPred;
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const int32_t kiStride2 = kiStride << 1;
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const int32_t kiStride3 = kiStride + kiStride2;
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int32_t i;
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for (i = 0; i < 4; i++) {
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const int32_t kiY = i << 2;
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const int32_t kiT0 = pRs[kiY] + pRs[kiY + 2];
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const int32_t kiT1 = pRs[kiY] - pRs[kiY + 2];
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const int32_t kiT2 = (pRs[kiY + 1] >> 1) - pRs[kiY + 3];
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const int32_t kiT3 = pRs[kiY + 1] + (pRs[kiY + 3] >> 1);
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iSrc[kiY] = kiT0 + kiT3;
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iSrc[kiY + 1] = kiT1 + kiT2;
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iSrc[kiY + 2] = kiT1 - kiT2;
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iSrc[kiY + 3] = kiT0 - kiT3;
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}
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for (i = 0; i < 4; i++) {
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int32_t kT1 = iSrc[i] + iSrc[i + 8];
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int32_t kT2 = iSrc[i + 4] + (iSrc[i + 12] >> 1);
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int32_t kT3 = (32 + kT1 + kT2) >> 6;
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int32_t kT4 = (32 + kT1 - kT2) >> 6;
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pDst[i] = WelsClip1 (kT3 + pPred[i]);
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pDst[i + kiStride3] = WelsClip1 (kT4 + pPred[i + kiStride3]);
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kT1 = iSrc[i] - iSrc[i + 8];
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kT2 = (iSrc[i + 4] >> 1) - iSrc[i + 12];
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pDst[i + kiStride] = WelsClip1 (((32 + kT1 + kT2) >> 6) + pDst[i + kiStride]);
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pDst[i + kiStride2] = WelsClip1 (((32 + kT1 - kT2) >> 6) + pDst[i + kiStride2]);
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}
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}
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void SetNonZeroCount_ref (int8_t* pNonZeroCount) {
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int32_t i;
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for (i = 0; i < 24; i++) {
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pNonZeroCount[i] = !!pNonZeroCount[i];
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}
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}
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#if defined(X86_ASM)
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void IdctFourResAddPred_ref (uint8_t* pPred, int32_t iStride, int16_t* pRs) {
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IdctResAddPred_ref (pPred + 0 * iStride + 0, iStride, pRs + 0 * 16);
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IdctResAddPred_ref (pPred + 0 * iStride + 4, iStride, pRs + 1 * 16);
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IdctResAddPred_ref (pPred + 4 * iStride + 0, iStride, pRs + 2 * 16);
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IdctResAddPred_ref (pPred + 4 * iStride + 4, iStride, pRs + 3 * 16);
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}
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#endif
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} // anon ns
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#define GENERATE_IDCTRESADDPRED(pred, flag) \
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TEST(DecoderDecodeMbAux, pred) {\
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const int32_t kiStride = 32;\
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const int iBits = 12;\
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const int iMask = (1 << iBits) - 1;\
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const int iOffset = 1 << (iBits - 1);\
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ENFORCE_STACK_ALIGN_1D (int16_t, iRS, 16, 16);\
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ENFORCE_STACK_ALIGN_1D (uint8_t, uiPred, 16 * kiStride, 16);\
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int16_t iRefRS[16];\
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uint8_t uiRefPred[16*kiStride];\
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int32_t iRunTimes = 1000;\
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uint32_t uiCPUFlags = WelsCPUFeatureDetect(NULL); \
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if ((uiCPUFlags & flag) == 0 && flag != 0) \
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return; \
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while(iRunTimes--) {\
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for(int i = 0; i < 4; i++)\
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for(int j = 0; j < 4; j++)\
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iRefRS[i*4+j] = iRS[i*4+j] = (rand() & iMask) - iOffset;\
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for(int i = 0; i < 4; i++)\
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for(int j = 0; j < 4; j++)\
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uiRefPred[i * kiStride + j] = uiPred[i * kiStride + j] = rand() & 255;\
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pred(uiPred, kiStride, iRS);\
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IdctResAddPred_ref(uiRefPred, kiStride, iRefRS);\
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bool ok = true;\
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for(int i = 0; i < 4; i++)\
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for(int j = 0; j < 4; j++)\
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if (uiRefPred[i * kiStride + j] != uiPred[i * kiStride + j]) {\
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ok = false;\
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goto next;\
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}\
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next:\
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EXPECT_EQ(ok, true);\
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}\
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}
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#define GENERATE_IDCTFOURRESADDPRED(pred, flag) \
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TEST(DecoderDecodeMbAux, pred) {\
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const int32_t kiStride = 32;\
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const int iBits = 12;\
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const int iMask = (1 << iBits) - 1;\
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const int iOffset = 1 << (iBits - 1);\
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ENFORCE_STACK_ALIGN_1D (int16_t, iRS, 4 * 16, 16);\
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ENFORCE_STACK_ALIGN_1D (uint8_t, uiPred, 4 * 16 * kiStride, 16);\
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int16_t iRefRS[4 * 16];\
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uint8_t uiRefPred[4 * 16 * kiStride];\
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int8_t iNzc[6] = { 0 };\
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int32_t iRunTimes = 1000;\
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uint32_t uiCPUFlags = WelsCPUFeatureDetect(0); \
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if ((uiCPUFlags & flag) == 0 && flag != 0) \
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return; \
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while (iRunTimes--) {\
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for (int i = 0; i < 4; i++)\
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for (int j = 0; j < 16; j++)\
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iNzc[i / 2 * 4 + i % 2] += !!(iRefRS[16 * i + j] = iRS[16 * i + j] = (rand() & iMask) - iOffset);\
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for (int i = 0; i < 8; i++)\
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for (int j = 0; j < 8; j++)\
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uiRefPred[i * kiStride + j] = uiPred[i * kiStride + j] = rand() & 255;\
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pred (uiPred, kiStride, iRS, iNzc);\
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IdctFourResAddPred_ref (uiRefPred, kiStride, iRefRS);\
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bool ok = true;\
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for (int i = 0; i < 8; i++)\
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for (int j = 0; j < 8; j++)\
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if (uiRefPred[i * kiStride + j] != uiPred[i * kiStride + j]) {\
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ok = false;\
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goto next;\
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}\
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next:\
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EXPECT_EQ(ok, true);\
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}\
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}
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GENERATE_IDCTRESADDPRED (IdctResAddPred_c, 0)
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#if defined(X86_ASM)
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GENERATE_IDCTRESADDPRED (IdctResAddPred_mmx, WELS_CPU_MMXEXT)
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GENERATE_IDCTRESADDPRED (IdctResAddPred_sse2, WELS_CPU_SSE2)
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GENERATE_IDCTRESADDPRED (IdctResAddPred_avx2, WELS_CPU_AVX2)
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GENERATE_IDCTFOURRESADDPRED (IdctFourResAddPred_avx2, WELS_CPU_AVX2)
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#endif
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#if defined(HAVE_NEON)
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GENERATE_IDCTRESADDPRED (IdctResAddPred_neon, WELS_CPU_NEON)
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#endif
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#if defined(HAVE_NEON_AARCH64)
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GENERATE_IDCTRESADDPRED (IdctResAddPred_AArch64_neon, WELS_CPU_NEON)
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#endif
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#define GENERATE_SETNONZEROCOUNT(method, flag) \
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TEST(DecoderDecodeMbAux, method) \
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{\
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uint32_t uiCPUFlags = WelsCPUFeatureDetect(NULL); \
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if ((uiCPUFlags & flag) == 0 && flag != 0) \
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return; \
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int8_t iNonZeroCount[2][24];\
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for(int32_t i = 0; i < 24; i++) {\
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iNonZeroCount[0][i] = iNonZeroCount[1][i] = (rand() % 25);\
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}\
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method(iNonZeroCount[0]);\
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SetNonZeroCount_ref(iNonZeroCount[1]);\
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for(int32_t i =0; i<24; i++) {\
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ASSERT_EQ (iNonZeroCount[0][i], iNonZeroCount[1][i]);\
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}\
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for(int32_t i =0; i<24; i++) {\
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iNonZeroCount[0][i] = iNonZeroCount[1][i] = 0;\
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}\
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method(iNonZeroCount[0]);\
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SetNonZeroCount_ref(iNonZeroCount[1]);\
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for(int32_t i =0; i<24; i++) {\
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ASSERT_EQ (iNonZeroCount[0][i], iNonZeroCount[1][i]);\
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}\
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for(int32_t i =0; i<24; i++) {\
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iNonZeroCount[0][i] = iNonZeroCount[1][i] = 16;\
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}\
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method(iNonZeroCount[0]);\
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SetNonZeroCount_ref(iNonZeroCount[1]);\
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for(int32_t i =0; i<24; i++) {\
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ASSERT_EQ (iNonZeroCount[0][i], iNonZeroCount[1][i]);\
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}\
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}
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GENERATE_SETNONZEROCOUNT (WelsNonZeroCount_c, 0)
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#if defined(X86_ASM)
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GENERATE_SETNONZEROCOUNT (WelsNonZeroCount_sse2, WELS_CPU_SSE2)
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#endif
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#if defined(HAVE_NEON)
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GENERATE_SETNONZEROCOUNT (WelsNonZeroCount_neon, WELS_CPU_NEON)
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#endif
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#if defined(HAVE_NEON_AARCH64)
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GENERATE_SETNONZEROCOUNT (WelsNonZeroCount_AArch64_neon, WELS_CPU_NEON)
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#endif
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