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1246 Commits

Author SHA1 Message Date
HaiboZhu
ad9ca3824f Merge pull request #2354 from ruil2/remove_trace 
fix error width and height issue
 2016-02-04 12:00:20 +08:00
Karina
ae508b9724 fix error width and height issue 2016-02-04 10:25:03 +08:00
sijchen
f5fd7420a9 Merge pull request #2351 from huili2/fix_width_height_enc_constraint 
fix frame size constraints for width and height
 2016-02-02 16:31:05 -08:00
Karina
2d4cbcf060 remove trace 2016-02-02 17:34:59 +08:00
unknown
3873addc3d fix frame size constraints for width and height 2016-02-01 15:55:53 +08:00
HaiboZhu
1030820ec4 Merge pull request #2342 from sijchen/enh_ut_tem 
[UT] correct and enhance the ut template and trace improvement
 2016-02-01 09:08:05 +08:00
sijchen
ef329e33c3 add simulcastAvc setting in setting trace 2016-01-20 14:24:16 -08:00
Sindre Aamås
e22d731f26 [Encoder] yasm-compatible vinserti128 syntax in DCT asm 2016-01-19 21:48:23 +01:00
Sindre Aamås
144ff0fd51 [Encoder] SSE2 4x4 IDCT optimizations 
Use a combination of instruction types that distributes more
evenly across execution ports on common architectures.

Do the horizontal IDCT without transposing back and forth.

Minor tweaks.

~1.14x faster on Haswell. Should be faster on other architectures
as well.
 2016-01-19 13:12:29 +01:00
Sindre Aamås
991e344d8c [Encoder] SSE2 4x4 DCT optimizations 
Use a combination of instruction types that distributes more
evenly across execution ports on common architectures.

Do the horizontal DCT without transposing back and forth.

Minor tweaks.

~1.54x faster on Haswell. Should be faster on other architectures
as well.
 2016-01-19 13:12:28 +01:00
Sindre Aamås
3088d96978 [Encoder] Add an AVX2 4x4 IDCT implementation 
~2.03x faster on Haswell as compared to the SSE2 version.
 2016-01-19 13:12:28 +01:00
Sindre Aamås
b267163f10 [Encoder] Add an AVX2 4x4 DCT implementation 
~2.52x faster on Haswell as compared to the SSE2 version.
 2016-01-19 13:12:28 +01:00
Martin Storsjö
fbe35cffca Avoid warnings in MSVC about implicitly casting floats to integers 2016-01-16 11:10:25 +02:00
HaiboZhu
d11f12db54 Merge pull request #2330 from ruil2/mt_build_1 
fix build issue when some macro turn on
 2016-01-15 09:28:07 +08:00
Karina
67f4dcf2e2 fix build issue when some macro turn on 2016-01-14 09:40:20 +08:00
Karina
0f0d54ef51 using independent encoder control logic for SAVC case 2016-01-14 09:16:12 +08:00
sijchen
5cad0f9bba enhance a UT to cover more case 2016-01-11 22:01:02 -08:00
sijchen
bf35b6fee7 add a debug trace if encoder returns error 2016-01-11 22:00:24 -08:00
sijchen
19f5eb0932 complete a debug trace in load-balancing task 2016-01-11 22:00:14 -08:00
sijchen
7a8da6a468 remove unneed codes after new task-managements 2016-01-11 21:59:49 -08:00
sijchen
dcdd496082 fix a bug in multi-layer case in task-management 2016-01-11 21:58:10 -08:00
HaiboZhu
b940e2cdf8 Merge pull request #2325 from ruil2/trace1 
separate each layer trace output
 2016-01-11 14:05:55 +08:00
ruil2
c32263e06b Merge pull request #2322 from HaiboZhu/Fix_Encoder_Info_Output 
Fix the build errors when open the encoder info output
 2016-01-08 17:15:15 +08:00
Karina
d4f979c495 seperate each layer trace output 2016-01-05 14:02:58 +08:00
Karina
57c87f1845 update format 2016-01-05 11:40:59 +08:00
Haibo Zhu
a6a504f944 Fix the build errors when open the encoder info output 2015-12-31 09:06:59 +08:00
Karina
0d5db3d986 resolve abnormal timestamp(rollback or jump case) 2015-12-29 15:05:42 +08:00
huade
f161566458 remove pSliceBs from ctx 2015-12-15 17:10:52 +08:00
huade
ef38c2abf8 refact threadIdc and CPU cores logic in init module 2015-12-15 11:27:00 +08:00
sijchen
406f89ec54 Merge pull request #2309 from shihuade/MultiThread_V4.4_ThreadSliceNum_V3_Pull 
remove iCountThreadsNum and unitfy with iMultipleThreadIdc
 2015-12-14 09:44:13 -08:00
huade
549a1b9bf4 fixed layer size update bugs 2015-12-14 14:56:09 +08:00
huade
e8536c6b73 remove iCountThreadsNum and unitfy with iMultipleThreadIdc 2015-12-14 12:26:02 +08:00
HaiboZhu
762d1812bb Merge pull request #2306 from shihuade/MultiThread_V4.4_ThreadSliceNum_V2_Pull 
refact validate and init logic for fixed sliceMode
 2015-12-14 09:44:38 +08:00
HaiboZhu
92637b4912 Merge pull request #2304 from sijchen/th21 
[Encoder] Add tasks and thread pool call for SM_SIZELIMITED_SLICE mode
 2015-12-11 16:16:16 +08:00
huade
14d89eb48c refact validate and init logic for fixed sliceMode 2015-12-11 13:08:05 +08:00
Karina
fde8bd2554 update temporal layer quant 2015-12-10 15:07:19 +08:00
sijchen
76ca56498a Add tasks and thread pool call for SM_SIZELIMITED_SLICE mode 2015-12-09 09:55:04 -08:00
huade
dcfe76d1ff unitfy slice bs writing for multi-thread(sliceindex==0 is the same with others ) 2015-12-08 14:09:43 +08:00
Karina
5ac58e8dc9 add parameter output trace 2015-12-03 16:47:57 +08:00
HaiboZhu
ece95c815c Merge pull request #2286 from sijchen/ut3 
[Encoder] adjust the input para judgement of iMaxNalSize
 2015-12-01 15:24:02 +08:00
sijchen
89752ff62f Refactor: remove CWelsTaskManageMultiD 2015-11-30 10:32:48 -08:00
HaiboZhu
f679da900f Merge pull request #2281 from sijchen/th11 
[Encoder] remove duplicated operation after thread pool
 2015-11-27 12:13:33 +08:00
HaiboZhu
b749fe7160 Merge pull request #2273 from sijchen/th0 
[Encoder] use different task when load-balancing or not, to save computation
 2015-11-27 09:29:22 +08:00
HaiboZhu
921443ead8 Merge pull request #2272 from sijchen/rf0 
[Encoder] put duplicated codes into one function
 2015-11-27 09:27:37 +08:00
huade
436da21ccf initial for iReturn and refact PPS Sps bs write function 2015-11-26 14:06:01 +08:00
huade
4a4ade1201 refact WriteSliceBs() 2015-11-26 09:32:33 +08:00
sijchen
8667452940 adjust the input para judgement of iMaxNalSize 2015-11-25 14:21:32 -08:00
sijchen
05c89b75f0 remove duplicated operation after thread pool and rename a task for clearer meaning 2015-11-25 13:46:21 -08:00
huade
d02addd90f remove pCountMbNumInSlice from SSliceCtx 2015-11-25 13:36:37 +08:00
HaiboZhu
f47be08065 Merge pull request #2271 from sijchen/rf1 
[Encoder] refactor multi-thread logic and add error-dealing
 2015-11-25 12:04:00 +08:00