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1264 Commits

Author SHA1 Message Date
sijchen
74955c877f set pointers to null and call uninit 2016-02-17 10:07:33 -08:00
sijchen
cc675f9fd1 add error handling in memory allocation failed case 2016-02-17 10:07:33 -08:00
ruil2
a26955e444 Merge pull request #2358 from sijchen/fix_free2 
[Encoder]  avoid memory problem if mem alloc failed in the middle of InitDqLayer
 2016-02-16 10:47:23 +08:00
sijchen
b76a79c726 move the rc free to the correct condition to avoid access to invalid memory 2016-02-15 10:13:50 -08:00
sijchen
025500d5aa move the assigning m_uiSpatialPicNum earlier to cover the memory leak if error in allocating pic 2016-02-15 10:13:23 -08:00
sijchen
36722c553b use WelsMallocz instead of WelsMalloc to avoid non-null pointer at init 2016-02-15 10:12:44 -08:00
sijchen
6a0f0811ae use WelsUninitEncoderExt in all free process in WelsInitEncoderExt 2016-02-15 10:06:43 -08:00
sijchen
408b7cad17 use WelsUninitEncoderExt rather than FreeMemorySvc which correctly deals with release of vpp memory 2016-02-15 10:04:52 -08:00
sijchen
2b9a250fbd include the free-ing of pointer into FreeDqLayer 2016-02-12 16:23:57 -08:00
sijchen
a1a3873a62 improve the code structure 2016-02-10 22:25:41 -08:00
sijchen
43fdf74fa6 fix a miss of assigning and remove an unused line 2016-02-10 21:54:53 -08:00
sijchen
914302a462 avoid memory problem if mem alloc failed in the middle of InitDqLayer 2016-02-10 21:54:53 -08:00
sijchen
aaa25160ec Merge pull request #2353 from saamas/encoder-x86-dct-opt2 
[Encoder] x86 DCT optimizations
 2016-02-08 15:00:12 -08:00
sijchen
e5e7013b73 Merge pull request #2350 from sijchen/th00 
[Common] Add sink to IWelsTask
 2016-02-08 14:59:38 -08:00
HaiboZhu
ad9ca3824f Merge pull request #2354 from ruil2/remove_trace 
fix error width and height issue
 2016-02-04 12:00:20 +08:00
Karina
ae508b9724 fix error width and height issue 2016-02-04 10:25:03 +08:00
sijchen
f5fd7420a9 Merge pull request #2351 from huili2/fix_width_height_enc_constraint 
fix frame size constraints for width and height
 2016-02-02 16:31:05 -08:00
Sindre Aamås
c8c74903f8 [Encoder] Add single-block AVX2 4x4 DCT/IDCT routines 
We do four blocks at a time when possible, but need to handle
single blocks at a time for intra prediction.

~3.15x speedup over MMX for the DCT on Haswell.
~2.94x speedup over MMX for the IDCT on Haswell.

Returns diminish with increasing vector length because a larger
proportion of the time is spent on load/store/shuffling.
 2016-02-02 17:22:49 +01:00
Sindre Aamås
f90960983c [Encoder] Add single-block SSE2 4x4 DCT/IDCT routines 
We do four blocks at a time when possible, but need to handle
single blocks at a time for intra prediction.

~2.31x speedup over MMX for the DCT on Haswell.
~1.92x speedup over MMX for the IDCT on Haswell.
 2016-02-02 17:22:48 +01:00
Sindre Aamås
7486de2844 [Encoder] AVX2 DCT tweaks 
Do some shuffling in load/store unpack/pack to save some
work in horizontal DCTs.

Use a few 128-bit broadcasts to compact data vectors a bit.

~1.04x speedup for the DCT case on Haswell.
~1.12x speedup for the IDCT case on Haswell.
 2016-02-02 17:22:48 +01:00
Karina
2d4cbcf060 remove trace 2016-02-02 17:34:59 +08:00
unknown
3873addc3d fix frame size constraints for width and height 2016-02-01 15:55:53 +08:00
HaiboZhu
1030820ec4 Merge pull request #2342 from sijchen/enh_ut_tem 
[UT] correct and enhance the ut template and trace improvement
 2016-02-01 09:08:05 +08:00
sijchen
ef329e33c3 add simulcastAvc setting in setting trace 2016-01-20 14:24:16 -08:00
Sindre Aamås
e22d731f26 [Encoder] yasm-compatible vinserti128 syntax in DCT asm 2016-01-19 21:48:23 +01:00
Sindre Aamås
144ff0fd51 [Encoder] SSE2 4x4 IDCT optimizations 
Use a combination of instruction types that distributes more
evenly across execution ports on common architectures.

Do the horizontal IDCT without transposing back and forth.

Minor tweaks.

~1.14x faster on Haswell. Should be faster on other architectures
as well.
 2016-01-19 13:12:29 +01:00
Sindre Aamås
991e344d8c [Encoder] SSE2 4x4 DCT optimizations 
Use a combination of instruction types that distributes more
evenly across execution ports on common architectures.

Do the horizontal DCT without transposing back and forth.

Minor tweaks.

~1.54x faster on Haswell. Should be faster on other architectures
as well.
 2016-01-19 13:12:28 +01:00
Sindre Aamås
3088d96978 [Encoder] Add an AVX2 4x4 IDCT implementation 
~2.03x faster on Haswell as compared to the SSE2 version.
 2016-01-19 13:12:28 +01:00
Sindre Aamås
b267163f10 [Encoder] Add an AVX2 4x4 DCT implementation 
~2.52x faster on Haswell as compared to the SSE2 version.
 2016-01-19 13:12:28 +01:00
Martin Storsjö
fbe35cffca Avoid warnings in MSVC about implicitly casting floats to integers 2016-01-16 11:10:25 +02:00
HaiboZhu
d11f12db54 Merge pull request #2330 from ruil2/mt_build_1 
fix build issue when some macro turn on
 2016-01-15 09:28:07 +08:00
Karina
67f4dcf2e2 fix build issue when some macro turn on 2016-01-14 09:40:20 +08:00
Karina
0f0d54ef51 using independent encoder control logic for SAVC case 2016-01-14 09:16:12 +08:00
sijchen
cce1c29844 add sink to IWelsTask (for further enhancements) 2016-01-13 16:24:54 -08:00
sijchen
5cad0f9bba enhance a UT to cover more case 2016-01-11 22:01:02 -08:00
sijchen
bf35b6fee7 add a debug trace if encoder returns error 2016-01-11 22:00:24 -08:00
sijchen
19f5eb0932 complete a debug trace in load-balancing task 2016-01-11 22:00:14 -08:00
sijchen
7a8da6a468 remove unneed codes after new task-managements 2016-01-11 21:59:49 -08:00
sijchen
dcdd496082 fix a bug in multi-layer case in task-management 2016-01-11 21:58:10 -08:00
HaiboZhu
b940e2cdf8 Merge pull request #2325 from ruil2/trace1 
separate each layer trace output
 2016-01-11 14:05:55 +08:00
ruil2
c32263e06b Merge pull request #2322 from HaiboZhu/Fix_Encoder_Info_Output 
Fix the build errors when open the encoder info output
 2016-01-08 17:15:15 +08:00
Karina
d4f979c495 seperate each layer trace output 2016-01-05 14:02:58 +08:00
Karina
57c87f1845 update format 2016-01-05 11:40:59 +08:00
Haibo Zhu
a6a504f944 Fix the build errors when open the encoder info output 2015-12-31 09:06:59 +08:00
Karina
0d5db3d986 resolve abnormal timestamp(rollback or jump case) 2015-12-29 15:05:42 +08:00
huade
f161566458 remove pSliceBs from ctx 2015-12-15 17:10:52 +08:00
huade
ef38c2abf8 refact threadIdc and CPU cores logic in init module 2015-12-15 11:27:00 +08:00
sijchen
406f89ec54 Merge pull request #2309 from shihuade/MultiThread_V4.4_ThreadSliceNum_V3_Pull 
remove iCountThreadsNum and unitfy with iMultipleThreadIdc
 2015-12-14 09:44:13 -08:00
huade
549a1b9bf4 fixed layer size update bugs 2015-12-14 14:56:09 +08:00
huade
e8536c6b73 remove iCountThreadsNum and unitfy with iMultipleThreadIdc 2015-12-14 12:26:02 +08:00