Convert the arm assembly sources to unix newlines
This commit is contained in:
Martin Storsjö
parent
5bc4a39820
commit
03e0dcd814
@ -1,55 +1,55 @@
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/*!
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/*!
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* \copy
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* \copy
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* Copyright (c) 2013, Cisco Systems
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* Copyright (c) 2013, Cisco Systems
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* All rights reserved.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* Redistribution and use in source and binary forms, with or without
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||||||
* modification, are permitted provided that the following conditions
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* modification, are permitted provided that the following conditions
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||||||
* are met:
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* are met:
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||||||
*
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*
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||||||
* * Redistributions of source code must retain the above copyright
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* * Redistributions of source code must retain the above copyright
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||||||
* notice, this list of conditions and the following disclaimer.
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* notice, this list of conditions and the following disclaimer.
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||||||
*
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*
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||||||
* * Redistributions in binary form must reproduce the above copyright
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* * Redistributions in binary form must reproduce the above copyright
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||||||
* notice, this list of conditions and the following disclaimer in
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* the documentation and/or other materials provided with the
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* distribution.
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* distribution.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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||||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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||||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*
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*/
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*/
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#ifdef APPLE_IOS
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#ifdef APPLE_IOS
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.macro WELS_ASM_FUNC_BEGIN
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.macro WELS_ASM_FUNC_BEGIN
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.align 2
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.align 2
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.arm
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.arm
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.globl _$0
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.globl _$0
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_$0:
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_$0:
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.endm
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.endm
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#else
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#else
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.macro WELS_ASM_FUNC_BEGIN funcName
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.macro WELS_ASM_FUNC_BEGIN funcName
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.align 2
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.align 2
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.arm
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.arm
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.global \funcName
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.global \funcName
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\funcName:
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\funcName:
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.endm
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.endm
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#endif
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#endif
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.macro WELS_ASM_FUNC_END
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.macro WELS_ASM_FUNC_END
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mov pc, lr
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mov pc, lr
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.endm
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.endm
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File diff suppressed because it is too large
Load Diff
@ -1,203 +1,203 @@
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/*!
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/*!
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* \copy
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* \copy
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* Copyright (c) 2013, Cisco Systems
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* Copyright (c) 2013, Cisco Systems
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* All rights reserved.
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* All rights reserved.
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*
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*
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||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
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||||||
* modification, are permitted provided that the following conditions
|
* modification, are permitted provided that the following conditions
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||||||
* are met:
|
* are met:
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||||||
*
|
*
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||||||
* * Redistributions of source code must retain the above copyright
|
* * Redistributions of source code must retain the above copyright
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||||||
* notice, this list of conditions and the following disclaimer.
|
* notice, this list of conditions and the following disclaimer.
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||||||
*
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*
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||||||
* * Redistributions in binary form must reproduce the above copyright
|
* * Redistributions in binary form must reproduce the above copyright
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||||||
* notice, this list of conditions and the following disclaimer in
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* the documentation and/or other materials provided with the
|
* the documentation and/or other materials provided with the
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||||||
* distribution.
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* distribution.
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||||||
*
|
*
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||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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||||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*
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*/
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*/
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#ifdef HAVE_NEON
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#ifdef HAVE_NEON
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.text
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.text
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#include "arm_arch_common_macro.S"
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#include "arm_arch_common_macro.S"
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#ifdef APPLE_IOS
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#ifdef APPLE_IOS
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.macro ROW_TRANSFORM_1_STEP
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.macro ROW_TRANSFORM_1_STEP
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// { // input: src_d[0]~[3], output: e_q[0]~[3]; working: $8 $9
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// { // input: src_d[0]~[3], output: e_q[0]~[3]; working: $8 $9
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vaddl.s16 $4, $0, $2 //int32 e[i][0] = src[0] + src[2];
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vaddl.s16 $4, $0, $2 //int32 e[i][0] = src[0] + src[2];
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vsubl.s16 $5, $0, $2 //int32 e[i][1] = src[0] - src[2];
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vsubl.s16 $5, $0, $2 //int32 e[i][1] = src[0] - src[2];
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vshr.s16 $8, $1, #1
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vshr.s16 $8, $1, #1
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vshr.s16 $9, $3, #1
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vshr.s16 $9, $3, #1
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vsubl.s16 $6, $8, $3 //int32 e[i][2] = (src[1]>>1)-src[3];
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vsubl.s16 $6, $8, $3 //int32 e[i][2] = (src[1]>>1)-src[3];
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vaddl.s16 $7, $1, $9 //int32 e[i][3] = src[1] + (src[3]>>1);
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vaddl.s16 $7, $1, $9 //int32 e[i][3] = src[1] + (src[3]>>1);
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// }
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// }
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.endm
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.endm
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.macro TRANSFORM_4BYTES // both row & col transform used
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.macro TRANSFORM_4BYTES // both row & col transform used
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// { // output: f_q[0]~[3], input: e_q[0]~[3];
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// { // output: f_q[0]~[3], input: e_q[0]~[3];
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vadd.s32 $0, $4, $7 //int16 f[i][0] = e[i][0] + e[i][3];
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vadd.s32 $0, $4, $7 //int16 f[i][0] = e[i][0] + e[i][3];
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vadd.s32 $1, $5, $6 //int16 f[i][1] = e[i][1] + e[i][2];
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vadd.s32 $1, $5, $6 //int16 f[i][1] = e[i][1] + e[i][2];
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vsub.s32 $2, $5, $6 //int16 f[i][2] = e[i][1] - e[i][2];
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vsub.s32 $2, $5, $6 //int16 f[i][2] = e[i][1] - e[i][2];
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vsub.s32 $3, $4, $7 //int16 f[i][3] = e[i][0] - e[i][3];
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vsub.s32 $3, $4, $7 //int16 f[i][3] = e[i][0] - e[i][3];
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// }
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// }
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.endm
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.endm
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.macro COL_TRANSFORM_1_STEP
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.macro COL_TRANSFORM_1_STEP
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// { // input: src_q[0]~[3], output: e_q[0]~[3];
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// { // input: src_q[0]~[3], output: e_q[0]~[3];
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vadd.s32 $4, $0, $2 //int32 e[0][j] = f[0][j] + f[2][j];
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vadd.s32 $4, $0, $2 //int32 e[0][j] = f[0][j] + f[2][j];
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vsub.s32 $5, $0, $2 //int32 e[1][j] = f[0][j] - f[2][j];
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vsub.s32 $5, $0, $2 //int32 e[1][j] = f[0][j] - f[2][j];
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vshr.s32 $6, $1, #1
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vshr.s32 $6, $1, #1
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vshr.s32 $7, $3, #1
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vshr.s32 $7, $3, #1
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vsub.s32 $6, $6, $3 //int32 e[2][j] = (f[1][j]>>1) - f[3][j];
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vsub.s32 $6, $6, $3 //int32 e[2][j] = (f[1][j]>>1) - f[3][j];
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vadd.s32 $7, $1, $7 //int32 e[3][j] = f[1][j] + (f[3][j]>>1);
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vadd.s32 $7, $1, $7 //int32 e[3][j] = f[1][j] + (f[3][j]>>1);
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// }
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// }
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.endm
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.endm
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#else
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#else
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.macro ROW_TRANSFORM_1_STEP arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9
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.macro ROW_TRANSFORM_1_STEP arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9
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// { // input: src_d[0]~[3], output: e_q[0]~[3]; working: $8 $9
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// { // input: src_d[0]~[3], output: e_q[0]~[3]; working: $8 $9
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vaddl.s16 \arg4, \arg0, \arg2 //int32 e[i][0] = src[0] + src[2];
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vaddl.s16 \arg4, \arg0, \arg2 //int32 e[i][0] = src[0] + src[2];
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vsubl.s16 \arg5, \arg0, \arg2 //int32 e[i][1] = src[0] - src[2];
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vsubl.s16 \arg5, \arg0, \arg2 //int32 e[i][1] = src[0] - src[2];
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vshr.s16 \arg8, \arg1, #1
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vshr.s16 \arg8, \arg1, #1
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vshr.s16 \arg9, \arg3, #1
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vshr.s16 \arg9, \arg3, #1
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vsubl.s16 \arg6, \arg8, \arg3 //int32 e[i][2] = (src[1]>>1)-src[3];
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vsubl.s16 \arg6, \arg8, \arg3 //int32 e[i][2] = (src[1]>>1)-src[3];
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vaddl.s16 \arg7, \arg1, \arg9 //int32 e[i][3] = src[1] + (src[3]>>1);
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vaddl.s16 \arg7, \arg1, \arg9 //int32 e[i][3] = src[1] + (src[3]>>1);
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// }
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// }
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.endm
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.endm
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.macro TRANSFORM_4BYTES arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7 // both row & col transform used
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.macro TRANSFORM_4BYTES arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7 // both row & col transform used
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// { // output: f_q[0]~[3], input: e_q[0]~[3];
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// { // output: f_q[0]~[3], input: e_q[0]~[3];
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vadd.s32 \arg0, \arg4, \arg7 //int16 f[i][0] = e[i][0] + e[i][3];
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vadd.s32 \arg0, \arg4, \arg7 //int16 f[i][0] = e[i][0] + e[i][3];
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vadd.s32 \arg1, \arg5, \arg6 //int16 f[i][1] = e[i][1] + e[i][2];
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vadd.s32 \arg1, \arg5, \arg6 //int16 f[i][1] = e[i][1] + e[i][2];
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vsub.s32 \arg2, \arg5, \arg6 //int16 f[i][2] = e[i][1] - e[i][2];
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vsub.s32 \arg2, \arg5, \arg6 //int16 f[i][2] = e[i][1] - e[i][2];
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vsub.s32 \arg3, \arg4, \arg7 //int16 f[i][3] = e[i][0] - e[i][3];
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vsub.s32 \arg3, \arg4, \arg7 //int16 f[i][3] = e[i][0] - e[i][3];
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// }
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// }
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.endm
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.endm
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.macro COL_TRANSFORM_1_STEP arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
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.macro COL_TRANSFORM_1_STEP arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7
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// { // input: src_q[0]~[3], output: e_q[0]~[3];
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// { // input: src_q[0]~[3], output: e_q[0]~[3];
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vadd.s32 \arg4, \arg0, \arg2 //int32 e[0][j] = f[0][j] + f[2][j];
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vadd.s32 \arg4, \arg0, \arg2 //int32 e[0][j] = f[0][j] + f[2][j];
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vsub.s32 \arg5, \arg0, \arg2 //int32 e[1][j] = f[0][j] - f[2][j];
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vsub.s32 \arg5, \arg0, \arg2 //int32 e[1][j] = f[0][j] - f[2][j];
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vshr.s32 \arg6, \arg1, #1
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vshr.s32 \arg6, \arg1, #1
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vshr.s32 \arg7, \arg3, #1
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vshr.s32 \arg7, \arg3, #1
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vsub.s32 \arg6, \arg6, \arg3 //int32 e[2][j] = (f[1][j]>>1) - f[3][j];
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vsub.s32 \arg6, \arg6, \arg3 //int32 e[2][j] = (f[1][j]>>1) - f[3][j];
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vadd.s32 \arg7, \arg1, \arg7 //int32 e[3][j] = f[1][j] + (f[3][j]>>1);
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vadd.s32 \arg7, \arg1, \arg7 //int32 e[3][j] = f[1][j] + (f[3][j]>>1);
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// }
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// }
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.endm
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.endm
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#endif
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#endif
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// r0 int16_t* block,
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// r0 int16_t* block,
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// r1 int8_t* non_zero_count,
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// r1 int8_t* non_zero_count,
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WELS_ASM_FUNC_BEGIN SetNonZeroCount_neon
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WELS_ASM_FUNC_BEGIN SetNonZeroCount_neon
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vld1.64 {d0-d2}, [r1]
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vld1.64 {d0-d2}, [r1]
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vceq.s8 q0, q0, #0
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vceq.s8 q0, q0, #0
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vceq.s8 d2, d2, #0
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vceq.s8 d2, d2, #0
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vmvn q0, q0
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vmvn q0, q0
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vmvn d2, d2
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vmvn d2, d2
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vabs.s8 q0, q0
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vabs.s8 q0, q0
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vabs.s8 d2, d2
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vabs.s8 d2, d2
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vst1.64 {d0-d2}, [r1]
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vst1.64 {d0-d2}, [r1]
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WELS_ASM_FUNC_END
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WELS_ASM_FUNC_END
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// r0 int16_t * block,
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// r0 int16_t * block,
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// r1 int32_t stride
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// r1 int32_t stride
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WELS_ASM_FUNC_BEGIN WelsResBlockZero16x16_neon// can use for 256*sizeof(int16_t)
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WELS_ASM_FUNC_BEGIN WelsResBlockZero16x16_neon// can use for 256*sizeof(int16_t)
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push {r2}
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push {r2}
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mov r2, #16
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mov r2, #16
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// each row 16 elements, 16*sizeof(int16_t)
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// each row 16 elements, 16*sizeof(int16_t)
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// memset(ptr_dest, 0, 16*sizeof(int16_t));
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// memset(ptr_dest, 0, 16*sizeof(int16_t));
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// ptr_dest += stride;
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// ptr_dest += stride;
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lsl r1, r1, #1 // r1 = 2*r1
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lsl r1, r1, #1 // r1 = 2*r1
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veor.i16 q0, q0, q0
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veor.i16 q0, q0, q0
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veor.i16 q1, q1, q1
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veor.i16 q1, q1, q1
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block_zero_16x16_luma_loop:
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block_zero_16x16_luma_loop:
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vst1.i16 {q0, q1}, [r0], r1
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vst1.i16 {q0, q1}, [r0], r1
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subs r2, r2, #2
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subs r2, r2, #2
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vst1.i16 {q0, q1}, [r0], r1
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vst1.i16 {q0, q1}, [r0], r1
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bne block_zero_16x16_luma_loop
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bne block_zero_16x16_luma_loop
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pop {r2}
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pop {r2}
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WELS_ASM_FUNC_END
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WELS_ASM_FUNC_END
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WELS_ASM_FUNC_BEGIN WelsResBlockZero8x8_neon// can use for 64*sizeof(int16_t)
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WELS_ASM_FUNC_BEGIN WelsResBlockZero8x8_neon// can use for 64*sizeof(int16_t)
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push {r2}
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push {r2}
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mov r2, #8
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mov r2, #8
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// each row 8 elements, 8*sizeof(int16_t)
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// each row 8 elements, 8*sizeof(int16_t)
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// memset(ptr_dest, 0, 8*sizeof(int16_t));
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// memset(ptr_dest, 0, 8*sizeof(int16_t));
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// ptr_dest += stride;
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// ptr_dest += stride;
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lsl r1, r1, #1
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lsl r1, r1, #1
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veor.i16 q0, q0, q0
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veor.i16 q0, q0, q0
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block_zero_8x8_chma_loop:
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block_zero_8x8_chma_loop:
|
||||||
vst1.i16 {q0}, [r0], r1
|
vst1.i16 {q0}, [r0], r1
|
||||||
subs r2, r2, #2
|
subs r2, r2, #2
|
||||||
vst1.i16 {q0}, [r0], r1
|
vst1.i16 {q0}, [r0], r1
|
||||||
bne block_zero_8x8_chma_loop
|
bne block_zero_8x8_chma_loop
|
||||||
|
|
||||||
pop {r2}
|
pop {r2}
|
||||||
WELS_ASM_FUNC_END
|
WELS_ASM_FUNC_END
|
||||||
|
|
||||||
|
|
||||||
// uint8_t *pred, const int32_t stride, int16_t *rs
|
// uint8_t *pred, const int32_t stride, int16_t *rs
|
||||||
WELS_ASM_FUNC_BEGIN IdctResAddPred_neon
|
WELS_ASM_FUNC_BEGIN IdctResAddPred_neon
|
||||||
|
|
||||||
vld4.s16 {d0, d1, d2, d3}, [r2] // cost 3 cycles!
|
vld4.s16 {d0, d1, d2, d3}, [r2] // cost 3 cycles!
|
||||||
|
|
||||||
ROW_TRANSFORM_1_STEP d0, d1, d2, d3, q4, q5, q6, q7, d4, d5
|
ROW_TRANSFORM_1_STEP d0, d1, d2, d3, q4, q5, q6, q7, d4, d5
|
||||||
|
|
||||||
TRANSFORM_4BYTES q0, q1, q2, q3, q4, q5, q6, q7
|
TRANSFORM_4BYTES q0, q1, q2, q3, q4, q5, q6, q7
|
||||||
|
|
||||||
// transform element 32bits
|
// transform element 32bits
|
||||||
vtrn.s32 q0, q1 //[0 1 2 3]+[4 5 6 7]-->[0 4 2 6]+[1 5 3 7]
|
vtrn.s32 q0, q1 //[0 1 2 3]+[4 5 6 7]-->[0 4 2 6]+[1 5 3 7]
|
||||||
vtrn.s32 q2, q3 //[8 9 10 11]+[12 13 14 15]-->[8 12 10 14]+[9 13 11 15]
|
vtrn.s32 q2, q3 //[8 9 10 11]+[12 13 14 15]-->[8 12 10 14]+[9 13 11 15]
|
||||||
vswp d1, d4 //[0 4 2 6]+[8 12 10 14]-->[0 4 8 12]+[2 6 10 14]
|
vswp d1, d4 //[0 4 2 6]+[8 12 10 14]-->[0 4 8 12]+[2 6 10 14]
|
||||||
vswp d3, d6 //[1 5 3 7]+[9 13 11 15]-->[1 5 9 13]+[3 7 11 15]
|
vswp d3, d6 //[1 5 3 7]+[9 13 11 15]-->[1 5 9 13]+[3 7 11 15]
|
||||||
|
|
||||||
COL_TRANSFORM_1_STEP q0, q1, q2, q3, q4, q5, q6, q7
|
COL_TRANSFORM_1_STEP q0, q1, q2, q3, q4, q5, q6, q7
|
||||||
|
|
||||||
TRANSFORM_4BYTES q0, q1, q2, q3, q4, q5, q6, q7
|
TRANSFORM_4BYTES q0, q1, q2, q3, q4, q5, q6, q7
|
||||||
|
|
||||||
//after clip_table[MAX_NEG_CROP] into [0, 255]
|
//after clip_table[MAX_NEG_CROP] into [0, 255]
|
||||||
mov r2, r0
|
mov r2, r0
|
||||||
vld1.32 {d12[0]},[r0],r1
|
vld1.32 {d12[0]},[r0],r1
|
||||||
vld1.32 {d12[1]},[r0],r1
|
vld1.32 {d12[1]},[r0],r1
|
||||||
vld1.32 {d14[0]},[r0],r1
|
vld1.32 {d14[0]},[r0],r1
|
||||||
vld1.32 {d14[1]},[r0]
|
vld1.32 {d14[1]},[r0]
|
||||||
|
|
||||||
vrshrn.s32 d8, q0, #6
|
vrshrn.s32 d8, q0, #6
|
||||||
vrshrn.s32 d9, q1, #6
|
vrshrn.s32 d9, q1, #6
|
||||||
vrshrn.s32 d10, q2, #6
|
vrshrn.s32 d10, q2, #6
|
||||||
vrshrn.s32 d11, q3, #6
|
vrshrn.s32 d11, q3, #6
|
||||||
|
|
||||||
vmovl.u8 q0,d12
|
vmovl.u8 q0,d12
|
||||||
vmovl.u8 q1,d14
|
vmovl.u8 q1,d14
|
||||||
vadd.s16 q0,q4
|
vadd.s16 q0,q4
|
||||||
vadd.s16 q1,q5
|
vadd.s16 q1,q5
|
||||||
|
|
||||||
vqmovun.s16 d12,q0
|
vqmovun.s16 d12,q0
|
||||||
vqmovun.s16 d14,q1
|
vqmovun.s16 d14,q1
|
||||||
|
|
||||||
vst1.32 {d12[0]},[r2],r1
|
vst1.32 {d12[0]},[r2],r1
|
||||||
vst1.32 {d12[1]},[r2],r1
|
vst1.32 {d12[1]},[r2],r1
|
||||||
vst1.32 {d14[0]},[r2],r1
|
vst1.32 {d14[0]},[r2],r1
|
||||||
vst1.32 {d14[1]},[r2]
|
vst1.32 {d14[1]},[r2]
|
||||||
WELS_ASM_FUNC_END
|
WELS_ASM_FUNC_END
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user