2014-04-17 04:06:48 +02:00
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/*!
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* \copy
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* Copyright (c) 2013, Cisco Systems
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifdef HAVE_NEON
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.text
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#include "arm_arch_common_macro.S"
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#ifdef __APPLE__
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2014-05-31 12:28:46 +02:00
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.macro LOAD_ALIGNED_DATA_WITH_STRIDE
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2014-04-17 04:06:48 +02:00
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// { // input: $0~$3, src*, src_stride
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vld1.64 {$0}, [$4,:128], $5
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vld1.64 {$1}, [$4,:128], $5
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vld1.64 {$2}, [$4,:128], $5
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vld1.64 {$3}, [$4,:128], $5
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// }
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.endm
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2014-05-31 12:28:46 +02:00
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.macro STORE_ALIGNED_DATA_WITH_STRIDE
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2014-04-17 04:06:48 +02:00
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// { // input: $0~$3, dst*, dst_stride
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vst1.64 {$0}, [$4,:128], $5
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vst1.64 {$1}, [$4,:128], $5
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vst1.64 {$2}, [$4,:128], $5
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vst1.64 {$3}, [$4,:128], $5
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// }
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.endm
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2014-05-31 12:28:46 +02:00
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.macro LOAD_UNALIGNED_DATA_WITH_STRIDE
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2014-04-17 04:06:48 +02:00
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// { // input: $0~$3, src*, src_stride
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vld1.64 {$0}, [$4], $5
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vld1.64 {$1}, [$4], $5
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vld1.64 {$2}, [$4], $5
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vld1.64 {$3}, [$4], $5
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// }
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.endm
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2014-05-31 12:28:46 +02:00
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.macro STORE_UNALIGNED_DATA_WITH_STRIDE
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2014-04-17 04:06:48 +02:00
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// { // input: $0~$3, dst*, dst_stride
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vst1.64 {$0}, [$4], $5
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vst1.64 {$1}, [$4], $5
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vst1.64 {$2}, [$4], $5
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vst1.64 {$3}, [$4], $5
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// }
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.endm
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#else
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2014-05-31 12:28:46 +02:00
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.macro LOAD_ALIGNED_DATA_WITH_STRIDE arg0, arg1, arg2, arg3, arg4, arg5
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2014-04-17 04:06:48 +02:00
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// { // input: \arg0~\arg3, src*, src_stride
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vld1.64 {\arg0}, [\arg4,:128], \arg5
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vld1.64 {\arg1}, [\arg4,:128], \arg5
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vld1.64 {\arg2}, [\arg4,:128], \arg5
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vld1.64 {\arg3}, [\arg4,:128], \arg5
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// }
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.endm
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2014-05-31 12:28:46 +02:00
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.macro STORE_ALIGNED_DATA_WITH_STRIDE arg0, arg1, arg2, arg3, arg4, arg5
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2014-04-17 04:06:48 +02:00
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// { // input: \arg0~\arg3, dst*, dst_stride
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vst1.64 {\arg0}, [\arg4,:128], \arg5
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vst1.64 {\arg1}, [\arg4,:128], \arg5
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vst1.64 {\arg2}, [\arg4,:128], \arg5
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vst1.64 {\arg3}, [\arg4,:128], \arg5
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// }
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.endm
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2014-05-31 12:28:46 +02:00
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.macro LOAD_UNALIGNED_DATA_WITH_STRIDE arg0, arg1, arg2, arg3, arg4, arg5
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2014-04-17 04:06:48 +02:00
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// { // input: \arg0~\arg3, src*, src_stride
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vld1.64 {\arg0}, [\arg4], \arg5
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vld1.64 {\arg1}, [\arg4], \arg5
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vld1.64 {\arg2}, [\arg4], \arg5
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vld1.64 {\arg3}, [\arg4], \arg5
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// }
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.endm
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2014-05-31 12:28:46 +02:00
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.macro STORE_UNALIGNED_DATA_WITH_STRIDE arg0, arg1, arg2, arg3, arg4, arg5
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2014-04-17 04:06:48 +02:00
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// { // input: \arg0~\arg3, dst*, dst_stride
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vst1.64 {\arg0}, [\arg4], \arg5
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vst1.64 {\arg1}, [\arg4], \arg5
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vst1.64 {\arg2}, [\arg4], \arg5
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vst1.64 {\arg3}, [\arg4], \arg5
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// }
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.endm
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#endif
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WELS_ASM_FUNC_BEGIN WelsCopy8x8_neon
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LOAD_UNALIGNED_DATA_WITH_STRIDE d0, d1, d2, d3, r2, r3
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STORE_UNALIGNED_DATA_WITH_STRIDE d0, d1, d2, d3, r0, r1
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LOAD_UNALIGNED_DATA_WITH_STRIDE d4, d5, d6, d7, r2, r3
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STORE_UNALIGNED_DATA_WITH_STRIDE d4, d5, d6, d7, r0, r1
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WELS_ASM_FUNC_END
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WELS_ASM_FUNC_BEGIN WelsCopy16x16_neon
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LOAD_ALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r2, r3
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STORE_ALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r0, r1
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LOAD_ALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r2, r3
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STORE_ALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r0, r1
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LOAD_ALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r2, r3
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STORE_ALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r0, r1
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LOAD_ALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r2, r3
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STORE_ALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r0, r1
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WELS_ASM_FUNC_END
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WELS_ASM_FUNC_BEGIN WelsCopy16x16NotAligned_neon
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LOAD_UNALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r2, r3
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STORE_UNALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r0, r1
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LOAD_UNALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r2, r3
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STORE_UNALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r0, r1
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LOAD_UNALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r2, r3
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STORE_UNALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r0, r1
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LOAD_UNALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r2, r3
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STORE_UNALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r0, r1
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WELS_ASM_FUNC_END
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WELS_ASM_FUNC_BEGIN WelsCopy16x8NotAligned_neon
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LOAD_UNALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r2, r3
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STORE_UNALIGNED_DATA_WITH_STRIDE q0, q1, q2, q3, r0, r1
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LOAD_UNALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r2, r3
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STORE_UNALIGNED_DATA_WITH_STRIDE q8, q9, q10, q11, r0, r1
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WELS_ASM_FUNC_END
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WELS_ASM_FUNC_BEGIN WelsCopy8x16_neon
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LOAD_UNALIGNED_DATA_WITH_STRIDE d0, d1, d2, d3, r2, r3
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STORE_UNALIGNED_DATA_WITH_STRIDE d0, d1, d2, d3, r0, r1
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LOAD_UNALIGNED_DATA_WITH_STRIDE d4, d5, d6, d7, r2, r3
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STORE_UNALIGNED_DATA_WITH_STRIDE d4, d5, d6, d7, r0, r1
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LOAD_UNALIGNED_DATA_WITH_STRIDE d0, d1, d2, d3, r2, r3
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STORE_UNALIGNED_DATA_WITH_STRIDE d0, d1, d2, d3, r0, r1
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LOAD_UNALIGNED_DATA_WITH_STRIDE d4, d5, d6, d7, r2, r3
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STORE_UNALIGNED_DATA_WITH_STRIDE d4, d5, d6, d7, r0, r1
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WELS_ASM_FUNC_END
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#endif
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