2014-03-04 09:49:34 +01:00
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/*!
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* \copy
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* Copyright (c) 2013, Cisco Systems
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifdef HAVE_NEON
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.text
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#include "arm_arch_common_macro.S"
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.macro SATD_16x4
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2014-03-05 09:54:05 +01:00
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vld1.64 {q0}, [r0,:128], r1
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vld1.64 {q1}, [r2], r3
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vsubl.u8 q4, d0, d2
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vld1.64 {q2}, [r0,:128], r1
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vsubl.u8 q6, d1, d3
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vld1.64 {q3}, [r2], r3
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vsubl.u8 q5, d4, d6
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vld1.64 {q0}, [r0,:128], r1
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vsubl.u8 q7, d5, d7
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2014-03-04 09:49:34 +01:00
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vld1.64 {q1}, [r2], r3
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vsubl.u8 q8, d0, d2
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2014-03-05 09:54:05 +01:00
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vld1.64 {q2}, [r0,:128], r1
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2014-03-04 09:49:34 +01:00
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vsubl.u8 q10, d1, d3
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2014-03-05 09:54:05 +01:00
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vadd.s16 q0, q4, q5
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vld1.64 {q3}, [r2], r3
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vsub.s16 q1, q4, q5
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vsubl.u8 q9, d4, d6
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vsubl.u8 q11, d5, d7
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vadd.s16 q2, q8, q9
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vsub.s16 q3, q8, q9
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vadd.s16 q4, q6, q7
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2014-03-04 09:49:34 +01:00
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vsub.s16 q5, q6, q7
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2014-03-05 09:54:05 +01:00
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vadd.s16 q6, q10, q11
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vsub.s16 q7, q10, q11
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vadd.s16 q8, q0, q2
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vsub.s16 q10, q0, q2
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vadd.s16 q9, q4, q6
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vsub.s16 q11, q4, q6
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vsub.s16 q0, q1, q3
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vadd.s16 q2, q1, q3
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vsub.s16 q1, q5, q7
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vadd.s16 q3, q5, q7
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vtrn.16 q8, q10
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vtrn.16 q9, q11
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vadd.s16 q4, q8, q10
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vabd.s16 q6, q8, q10
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vadd.s16 q5, q9, q11
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vabd.s16 q7, q9, q11
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2014-03-04 09:49:34 +01:00
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vabs.s16 q4, q4
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vabs.s16 q5, q5
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2014-03-05 09:54:05 +01:00
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vtrn.16 q0, q2
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vtrn.16 q1, q3
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vadd.s16 q8, q0, q2
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vabd.s16 q10, q0, q2
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vadd.s16 q9, q1, q3
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2014-03-04 09:49:34 +01:00
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vabd.s16 q11, q1, q3
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vabs.s16 q8, q8
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vabs.s16 q9, q9
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vtrn.32 q4, q6
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vtrn.32 q5, q7
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vtrn.32 q8, q10
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vtrn.32 q9, q11
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vmax.s16 q0, q4, q6
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vmax.s16 q1, q5, q7
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vmax.s16 q2, q8, q10
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vmax.s16 q3, q9, q11
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vadd.u16 q0, q0, q1
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vadd.u16 q2, q2, q3
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.endm
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.macro SATD_8x4
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vld1.64 {d0}, [r0,:64], r1
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vld1.64 {d1}, [r2], r3
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vld1.64 {d2}, [r0,:64], r1
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2014-03-05 09:54:05 +01:00
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vsubl.u8 q4, d0, d1
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2014-03-04 09:49:34 +01:00
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vld1.64 {d3}, [r2], r3
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2014-03-05 09:54:05 +01:00
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vsubl.u8 q5, d2, d3
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2014-03-04 09:49:34 +01:00
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vld1.64 {d4}, [r0,:64], r1
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vld1.64 {d5}, [r2], r3
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2014-03-05 09:54:05 +01:00
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vadd.s16 q8, q4, q5
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vsubl.u8 q6, d4, d5
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2014-03-04 09:49:34 +01:00
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vld1.64 {d6}, [r0,:64], r1
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vld1.64 {d7}, [r2], r3
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2014-03-05 09:54:05 +01:00
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vsubl.u8 q7, d6, d7
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vsub.s16 q9, q4, q5
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vadd.s16 q10, q6, q7
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vsub.s16 q11, q6, q7
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vadd.s16 q0, q8, q10
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vsub.s16 q1, q8, q10
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2014-03-04 09:49:34 +01:00
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2014-03-05 09:54:05 +01:00
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vsub.s16 q2, q9, q11
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vadd.s16 q3, q9, q11
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2014-03-04 09:49:34 +01:00
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vtrn.16 q0, q1
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vtrn.16 q2, q3
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vadd.s16 q4, q0, q1
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vabd.s16 q5, q0, q1
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vabs.s16 q4, q4
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vadd.s16 q6, q2, q3
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vabd.s16 q7, q2, q3
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vabs.s16 q6, q6
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vtrn.32 q4, q5
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vtrn.32 q6, q7
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vmax.s16 q0, q4, q5
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vmax.s16 q1, q6, q7
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.endm
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.macro SAD_16x4
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vld1.64 {q6}, [r0, :128], r1
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vabal.u8 q10, d8, d10
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vld1.64 {q7}, [r2], r3
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vabal.u8 q11, d9, d11
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vld1.64 {q0}, [r0, :128], r1
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vabal.u8 q12, d12, d14
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vld1.64 {q1}, [r2], r3
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vabal.u8 q13, d13, d15
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vld1.64 {q2}, [r0, :128], r1
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vabal.u8 q10, d0, d2
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vld1.64 {q3}, [r2], r3
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vabal.u8 q11, d1, d3
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vld1.64 {q4}, [r0, :128], r1
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vabal.u8 q12, d4, d6
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vld1.64 {q5}, [r2], r3
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vabal.u8 q13, d5, d7
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.endm
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.macro SAD_8x4
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vld1.64 {d0}, [r0, :64], r1
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vld1.64 {d1}, [r2], r3
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vabal.u8 q10, d0, d1
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vld1.64 {d2}, [r0, :64], r1
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vld1.64 {d3}, [r2], r3
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vabal.u8 q11, d2, d3
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vld1.64 {d4}, [r0, :64], r1
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vld1.64 {d5}, [r2], r3
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vabal.u8 q12, d4, d5
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vld1.64 {d6}, [r0, :64], r1
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vld1.64 {d7}, [r2], r3
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vabal.u8 q13, d6, d7
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.endm
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2014-03-05 09:54:05 +01:00
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WELS_ASM_FUNC_BEGIN WelsSampleSad16x16_neon
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2014-03-04 09:49:34 +01:00
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vld1.64 {q0}, [r0, :128], r1
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vld1.64 {q1}, [r2], r3
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vabdl.u8 q10, d0, d2
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vld1.64 {q2}, [r0, :128], r1
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vabdl.u8 q11, d1, d3
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vld1.64 {q3}, [r2], r3
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vld1.64 {q4}, [r0, :128], r1
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vabdl.u8 q12, d4, d6
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vld1.64 {q5}, [r2], r3
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vabdl.u8 q13, d5, d7
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SAD_16x4
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SAD_16x4
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SAD_16x4
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vld1.64 {q6}, [r0, :128], r1
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vabal.u8 q10, d8, d10
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vld1.64 {q7}, [r2], r3
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vabal.u8 q11, d9, d11
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vabal.u8 q12, d12, d14
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vabal.u8 q13, d13, d15
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vadd.u16 q14, q10, q11
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vadd.u16 q15, q12, q13
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vadd.u16 q15, q14, q15
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vadd.u16 d0, d30, d31
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vpaddl.u16 d0, d0
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vpaddl.u32 d0, d0
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vmov.u32 r0, d0[0]
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WELS_ASM_FUNC_END
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2014-03-05 09:54:05 +01:00
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WELS_ASM_FUNC_BEGIN WelsSampleSad16x8_neon
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2014-03-04 09:49:34 +01:00
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vld1.64 {q0}, [r0, :128], r1
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vld1.64 {q1}, [r2], r3
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vabdl.u8 q10, d0, d2
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vld1.64 {q2}, [r0, :128], r1
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vabdl.u8 q11, d1, d3
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vld1.64 {q3}, [r2], r3
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vld1.64 {q4}, [r0, :128], r1
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vabdl.u8 q12, d4, d6
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vld1.64 {q5}, [r2], r3
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vabdl.u8 q13, d5, d7
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SAD_16x4
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vld1.64 {q6}, [r0, :128], r1
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vabal.u8 q10, d8, d10
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vld1.64 {q7}, [r2], r3
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vabal.u8 q11, d9, d11
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vabal.u8 q12, d12, d14
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vabal.u8 q13, d13, d15
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vadd.u16 q14, q10, q11
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vadd.u16 q15, q12, q13
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vadd.u16 q15, q14, q15
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vadd.u16 d0, d30, d31
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vpaddl.u16 d0, d0
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vpaddl.u32 d0, d0
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vmov.u32 r0, d0[0]
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WELS_ASM_FUNC_END
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2014-03-05 09:54:05 +01:00
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WELS_ASM_FUNC_BEGIN WelsSampleSad8x16_neon
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2014-03-04 09:49:34 +01:00
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vld1.64 {d0}, [r0, :64], r1
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vld1.64 {d1}, [r2], r3
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vabdl.u8 q10, d0, d1
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vld1.64 {d2}, [r0, :64], r1
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vld1.64 {d3}, [r2], r3
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vabdl.u8 q11, d2, d3
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vld1.64 {d4}, [r0, :64], r1
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vld1.64 {d5}, [r2], r3
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vabdl.u8 q12, d4, d5
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vld1.64 {d6}, [r0, :64], r1
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vld1.64 {d7}, [r2], r3
|
|
|
|
vabdl.u8 q13, d6, d7
|
|
|
|
|
|
|
|
SAD_8x4
|
|
|
|
SAD_8x4
|
|
|
|
SAD_8x4
|
|
|
|
|
|
|
|
vadd.u16 q14, q10, q11
|
|
|
|
vadd.u16 q15, q12, q13
|
|
|
|
vadd.u16 q15, q15, q14
|
|
|
|
vadd.u16 d0, d30, d31
|
|
|
|
vpaddl.u16 d0, d0
|
|
|
|
vpaddl.u32 d0, d0
|
|
|
|
vmov.u32 r0, d0[0]
|
|
|
|
WELS_ASM_FUNC_END
|
|
|
|
|
|
|
|
|
2014-03-05 09:54:05 +01:00
|
|
|
WELS_ASM_FUNC_BEGIN WelsSampleSad8x8_neon
|
2014-03-04 09:49:34 +01:00
|
|
|
|
|
|
|
vld1.64 {d0}, [r0, :64], r1
|
|
|
|
vld1.64 {d1}, [r2], r3
|
|
|
|
|
|
|
|
vabdl.u8 q10, d0, d1
|
|
|
|
vld1.64 {d2}, [r0, :64], r1
|
|
|
|
|
|
|
|
vld1.64 {d3}, [r2], r3
|
|
|
|
vabdl.u8 q11, d2, d3
|
|
|
|
|
|
|
|
vld1.64 {d4}, [r0, :64], r1
|
|
|
|
vld1.64 {d5}, [r2], r3
|
|
|
|
|
|
|
|
vabdl.u8 q12, d4, d5
|
|
|
|
vld1.64 {d6}, [r0, :64], r1
|
|
|
|
|
|
|
|
vld1.64 {d7}, [r2], r3
|
|
|
|
vabdl.u8 q13, d6, d7
|
|
|
|
|
|
|
|
SAD_8x4
|
|
|
|
|
|
|
|
vadd.u16 q14, q10, q11
|
|
|
|
vadd.u16 q15, q12, q13
|
|
|
|
vadd.u16 q15, q15, q14
|
|
|
|
vadd.u16 d0, d30, d31
|
|
|
|
vpaddl.u16 d0, d0
|
|
|
|
vpaddl.u32 d0, d0
|
|
|
|
vmov.u32 r0, d0[0]
|
|
|
|
WELS_ASM_FUNC_END
|
|
|
|
|
|
|
|
|
2014-03-05 09:54:05 +01:00
|
|
|
WELS_ASM_FUNC_BEGIN WelsSampleSad4x4_neon
|
2014-03-04 09:49:34 +01:00
|
|
|
stmdb sp!, {r4-r5, lr}
|
|
|
|
|
|
|
|
//Loading a horizontal line data (4 bytes)
|
|
|
|
//line 0
|
|
|
|
ldr r4, [r0], r1
|
|
|
|
ldr r5, [r2], r3
|
|
|
|
usad8 lr, r4, r5
|
|
|
|
|
|
|
|
//line 1
|
|
|
|
ldr r4, [r0], r1
|
|
|
|
ldr r5, [r2], r3
|
2014-03-05 09:54:05 +01:00
|
|
|
usada8 lr, r4, r5, lr
|
2014-03-04 09:49:34 +01:00
|
|
|
|
2014-03-05 09:54:05 +01:00
|
|
|
//line 2
|
2014-03-04 09:49:34 +01:00
|
|
|
ldr r4, [r0], r1
|
|
|
|
ldr r5, [r2], r3
|
2014-03-05 09:54:05 +01:00
|
|
|
usada8 lr, r4, r5, lr
|
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
//line 3
|
|
|
|
ldr r4, [r0]
|
|
|
|
ldr r5, [r2]
|
2014-03-05 09:54:05 +01:00
|
|
|
usada8 r0, r4, r5, lr
|
2014-03-04 09:49:34 +01:00
|
|
|
|
|
|
|
ldmia sp!, {r4-r5, lr}
|
|
|
|
WELS_ASM_FUNC_END
|
|
|
|
|
|
|
|
|
2014-03-05 09:54:05 +01:00
|
|
|
WELS_ASM_FUNC_BEGIN WelsSampleSadFour16x16_neon
|
2014-03-04 09:49:34 +01:00
|
|
|
|
|
|
|
stmdb sp!, {r4-r5, lr}
|
|
|
|
|
|
|
|
//Generate the pix2 start addr
|
|
|
|
sub r4, r2, #1
|
|
|
|
add r5, r2, #1
|
|
|
|
sub r2, r3
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
//Loading a horizontal line data (16 bytes)
|
|
|
|
vld1.8 {q0}, [r0], r1 //save pix1
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vld1.8 {q1}, [r2], r3 //save pix2 - stride
|
|
|
|
vld1.8 {q6}, [r2], r3 //save pix2
|
|
|
|
vld1.8 {q2}, [r2], r3 //save pix2 + stride
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vld1.8 {q3}, [r4], r3 //save pix2 - 1
|
2014-03-05 09:54:05 +01:00
|
|
|
vld1.8 {q4}, [r5], r3 //save pix2 + 1
|
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
//Do the SAD for 16 bytes
|
|
|
|
vabdl.u8 q15, d0, d2
|
|
|
|
vabal.u8 q15, d1, d3
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vabdl.u8 q13, d0, d4
|
|
|
|
vabal.u8 q13, d1, d5
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vabdl.u8 q11, d0, d6
|
|
|
|
vabal.u8 q11, d1, d7
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vabdl.u8 q9, d0, d8
|
2014-03-05 09:54:05 +01:00
|
|
|
vabal.u8 q9, d1, d9
|
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
mov lr, #15
|
|
|
|
pixel_sad_4_16x16_loop_0:
|
|
|
|
|
|
|
|
//Loading a horizontal line data (16 bytes)
|
|
|
|
vld1.8 {q0}, [r0], r1 //save pix1
|
|
|
|
vmov.8 q1, q6 //save pix2 - stride
|
|
|
|
vmov.8 q6, q2
|
|
|
|
vabal.u8 q15, d0, d2
|
|
|
|
vld1.8 {q2}, [r2], r3 //save pix2 + stride
|
|
|
|
vabal.u8 q15, d1, d3
|
|
|
|
vld1.8 {q3}, [r4], r3 //save pix2 - 1
|
|
|
|
vabal.u8 q13, d0, d4
|
2014-03-05 09:54:05 +01:00
|
|
|
vld1.8 {q4}, [r5], r3 //save pix2 + 1
|
2014-03-04 09:49:34 +01:00
|
|
|
vabal.u8 q13, d1, d5
|
|
|
|
subs lr, #1
|
|
|
|
|
|
|
|
vabal.u8 q11, d0, d6
|
|
|
|
vabal.u8 q11, d1, d7
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vabal.u8 q9, d0, d8
|
|
|
|
vabal.u8 q9, d1, d9
|
|
|
|
|
|
|
|
bne pixel_sad_4_16x16_loop_0
|
|
|
|
|
|
|
|
|
|
|
|
//Save SAD to 'r0'
|
|
|
|
ldr r0, [sp, #12]
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vadd.u16 d0, d30, d31
|
|
|
|
vadd.u16 d1, d26, d27
|
|
|
|
vadd.u16 d2, d22, d23
|
|
|
|
vadd.u16 d3, d18, d19
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vpaddl.u16 q0, q0
|
|
|
|
vpaddl.u16 q1, q1
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vpaddl.u32 q0, q0
|
|
|
|
vpaddl.u32 q1, q1
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vst4.32 {d0[0],d1[0],d2[0],d3[0]}, [r0]
|
|
|
|
|
|
|
|
ldmia sp!, {r4-r5, lr}
|
|
|
|
WELS_ASM_FUNC_END
|
|
|
|
|
|
|
|
|
2014-03-05 09:54:05 +01:00
|
|
|
WELS_ASM_FUNC_BEGIN WelsSampleSadFour16x8_neon
|
2014-03-04 09:49:34 +01:00
|
|
|
stmdb sp!, {r4-r5, lr}
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
//Generate the pix2 start addr
|
|
|
|
sub r4, r2, #1
|
|
|
|
add r5, r2, #1
|
|
|
|
sub r2, r3
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
//Loading a horizontal line data (16 bytes)
|
|
|
|
vld1.8 {q0}, [r0], r1 //save pix1
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vld1.8 {q1}, [r2], r3 //save pix2 - stride
|
|
|
|
vld1.8 {q6}, [r2], r3 //save pix2
|
|
|
|
vld1.8 {q2}, [r2], r3 //save pix2 + stride
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vld1.8 {q3}, [r4], r3 //save pix2 - 1
|
2014-03-05 09:54:05 +01:00
|
|
|
vld1.8 {q4}, [r5], r3 //save pix2 + 1
|
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
//Do the SAD for 16 bytes
|
|
|
|
vabdl.u8 q15, d0, d2
|
|
|
|
vabal.u8 q15, d1, d3
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vabdl.u8 q13, d0, d4
|
|
|
|
vabal.u8 q13, d1, d5
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vabdl.u8 q11, d0, d6
|
|
|
|
vabal.u8 q11, d1, d7
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vabdl.u8 q9, d0, d8
|
2014-03-05 09:54:05 +01:00
|
|
|
vabal.u8 q9, d1, d9
|
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
mov lr, #7
|
|
|
|
pixel_sad_4_16x8_loop_0:
|
|
|
|
|
|
|
|
//Loading a horizontal line data (16 bytes)
|
|
|
|
vld1.8 {q0}, [r0], r1 //save pix1
|
|
|
|
vmov.8 q1, q6 //save pix2 - stride
|
|
|
|
vmov.8 q6, q2
|
|
|
|
vabal.u8 q15, d0, d2
|
|
|
|
vld1.8 {q2}, [r2], r3 //save pix2 + stride
|
|
|
|
vabal.u8 q15, d1, d3
|
|
|
|
vld1.8 {q3}, [r4], r3 //save pix2 - 1
|
|
|
|
vabal.u8 q13, d0, d4
|
2014-03-05 09:54:05 +01:00
|
|
|
vld1.8 {q4}, [r5], r3 //save pix2 + 1
|
2014-03-04 09:49:34 +01:00
|
|
|
vabal.u8 q13, d1, d5
|
|
|
|
subs lr, #1
|
|
|
|
|
|
|
|
vabal.u8 q11, d0, d6
|
|
|
|
vabal.u8 q11, d1, d7
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vabal.u8 q9, d0, d8
|
|
|
|
vabal.u8 q9, d1, d9
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
bne pixel_sad_4_16x8_loop_0
|
|
|
|
|
|
|
|
//Save SAD to 'r0'
|
|
|
|
ldr r0, [sp, #12]
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vadd.u16 d0, d30, d31
|
|
|
|
vadd.u16 d1, d26, d27
|
|
|
|
vadd.u16 d2, d22, d23
|
|
|
|
vadd.u16 d3, d18, d19
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vpaddl.u16 q0, q0
|
|
|
|
vpaddl.u16 q1, q1
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vpaddl.u32 q0, q0
|
|
|
|
vpaddl.u32 q1, q1
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vst4.32 {d0[0],d1[0],d2[0],d3[0]}, [r0]
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
ldmia sp!, {r4-r5, lr}
|
|
|
|
WELS_ASM_FUNC_END
|
|
|
|
|
2014-03-05 09:54:05 +01:00
|
|
|
|
|
|
|
WELS_ASM_FUNC_BEGIN WelsSampleSadFour8x16_neon
|
2014-03-04 09:49:34 +01:00
|
|
|
stmdb sp!, {r4-r5, lr}
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
//Generate the pix2 start addr
|
|
|
|
sub r4, r2, #1
|
|
|
|
add r5, r2, #1
|
|
|
|
sub r2, r3
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
//Loading a horizontal line data (8 bytes)
|
|
|
|
vld1.8 {d0}, [r0], r1 //save pix1
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vld1.8 {d1}, [r2], r3 //save pix2 - stride
|
|
|
|
vld1.8 {d6}, [r2], r3 //save pix2
|
|
|
|
vld1.8 {d2}, [r2], r3 //save pix2 + stride
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vld1.8 {d3}, [r4], r3 //save pix2 - 1
|
2014-03-05 09:54:05 +01:00
|
|
|
vld1.8 {d4}, [r5], r3 //save pix2 + 1
|
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
//Do the SAD for 8 bytes
|
|
|
|
vabdl.u8 q15, d0, d1
|
|
|
|
vabdl.u8 q14, d0, d2
|
|
|
|
vabdl.u8 q13, d0, d3
|
2014-03-05 09:54:05 +01:00
|
|
|
vabdl.u8 q12, d0, d4
|
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
mov lr, #15
|
|
|
|
pixel_sad_4_8x16_loop_0:
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
//Loading a horizontal line data (8 bytes)
|
|
|
|
vld1.8 {d0}, [r0], r1 //save pix1
|
|
|
|
vmov.8 d1, d6 //save pix2 - stride
|
|
|
|
vmov.8 d6, d2
|
|
|
|
vld1.8 {d2}, [r2], r3 //save pix2 + stride
|
|
|
|
vld1.8 {d3}, [r4], r3 //save pix2 - 1
|
|
|
|
vabal.u8 q15, d0, d1
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vld1.8 {d4}, [r5], r3 //save pix2 + 1
|
|
|
|
//Do the SAD for 8 bytes
|
|
|
|
vabal.u8 q14, d0, d2
|
|
|
|
vabal.u8 q13, d0, d3
|
|
|
|
vabal.u8 q12, d0, d4
|
|
|
|
subs lr, #1
|
|
|
|
|
|
|
|
bne pixel_sad_4_8x16_loop_0
|
|
|
|
|
|
|
|
//Save SAD to 'r0'
|
|
|
|
ldr r0, [sp, #12]
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vadd.u16 d0, d30, d31
|
|
|
|
vadd.u16 d1, d28, d29
|
|
|
|
vadd.u16 d2, d26, d27
|
|
|
|
vadd.u16 d3, d24, d25
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vpaddl.u16 q0, q0
|
|
|
|
vpaddl.u16 q1, q1
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vpaddl.u32 q0, q0
|
|
|
|
vpaddl.u32 q1, q1
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vst4.32 {d0[0],d1[0],d2[0],d3[0]}, [r0]
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
ldmia sp!, {r4-r5, lr}
|
|
|
|
WELS_ASM_FUNC_END
|
|
|
|
|
|
|
|
|
2014-03-05 09:54:05 +01:00
|
|
|
WELS_ASM_FUNC_BEGIN WelsSampleSadFour8x8_neon
|
2014-03-04 09:49:34 +01:00
|
|
|
stmdb sp!, {r4-r5, lr}
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
//Generate the pix2 start addr
|
|
|
|
sub r4, r2, #1
|
|
|
|
add r5, r2, #1
|
|
|
|
sub r2, r3
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
//Loading a horizontal line data (8 bytes)
|
|
|
|
vld1.8 {d0}, [r0], r1 //save pix1
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vld1.8 {d1}, [r2], r3 //save pix2 - stride
|
|
|
|
vld1.8 {d6}, [r2], r3 //save pix2
|
|
|
|
vld1.8 {d2}, [r2], r3 //save pix2 + stride
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vld1.8 {d3}, [r4], r3 //save pix2 - 1
|
2014-03-05 09:54:05 +01:00
|
|
|
vld1.8 {d4}, [r5], r3 //save pix2 + 1
|
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
//Do the SAD for 8 bytes
|
|
|
|
vabdl.u8 q15, d0, d1
|
|
|
|
vabdl.u8 q14, d0, d2
|
|
|
|
vabdl.u8 q13, d0, d3
|
2014-03-05 09:54:05 +01:00
|
|
|
vabdl.u8 q12, d0, d4
|
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
mov lr, #7
|
|
|
|
pixel_sad_4_8x8_loop_0:
|
|
|
|
|
|
|
|
//Loading a horizontal line data (8 bytes)
|
|
|
|
vld1.8 {d0}, [r0], r1 //save pix1
|
|
|
|
vmov.8 d1, d6 //save pix2 - stride
|
|
|
|
vmov.8 d6, d2
|
|
|
|
vld1.8 {d2}, [r2], r3 //save pix2 + stride
|
|
|
|
vld1.8 {d3}, [r4], r3 //save pix2 - 1
|
|
|
|
vabal.u8 q15, d0, d1
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vld1.8 {d4}, [r5], r3 //save pix2 + 1
|
|
|
|
//Do the SAD for 8 bytes
|
|
|
|
vabal.u8 q14, d0, d2
|
|
|
|
vabal.u8 q13, d0, d3
|
|
|
|
vabal.u8 q12, d0, d4
|
|
|
|
subs lr, #1
|
|
|
|
bne pixel_sad_4_8x8_loop_0
|
|
|
|
|
|
|
|
//Save SAD to 'r0'
|
|
|
|
ldr r0, [sp, #12]
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vadd.u16 d0, d30, d31
|
|
|
|
vadd.u16 d1, d28, d29
|
|
|
|
vadd.u16 d2, d26, d27
|
|
|
|
vadd.u16 d3, d24, d25
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vpaddl.u16 q0, q0
|
|
|
|
vpaddl.u16 q1, q1
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vpaddl.u32 q0, q0
|
|
|
|
vpaddl.u32 q1, q1
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vst4.32 {d0[0],d1[0],d2[0],d3[0]}, [r0]
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
ldmia sp!, {r4-r5, lr}
|
|
|
|
WELS_ASM_FUNC_END
|
|
|
|
|
|
|
|
|
2014-03-05 09:54:05 +01:00
|
|
|
WELS_ASM_FUNC_BEGIN WelsSampleSadFour4x4_neon
|
2014-03-04 09:49:34 +01:00
|
|
|
|
|
|
|
vld1.32 {d0[0]}, [r0], r1
|
|
|
|
vld1.32 {d0[1]}, [r0], r1
|
|
|
|
vld1.32 {d1[0]}, [r0], r1
|
|
|
|
vld1.32 {d1[1]}, [r0]
|
2014-03-05 09:54:05 +01:00
|
|
|
|
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
sub r0, r2, r3
|
|
|
|
vld1.32 {d2[0]}, [r0], r3
|
|
|
|
vld1.32 {d2[1]}, [r0], r3
|
|
|
|
vld1.32 {d3[0]}, [r0], r3
|
|
|
|
vld1.32 {d3[1]}, [r0], r3
|
|
|
|
vld1.32 {d4[0]}, [r0], r3
|
2014-03-05 09:54:05 +01:00
|
|
|
vld1.32 {d4[1]}, [r0]
|
|
|
|
|
|
|
|
sub r0, r2, #1
|
2014-03-04 09:49:34 +01:00
|
|
|
vld1.32 {d5[0]}, [r0], r3
|
|
|
|
vld1.32 {d5[1]}, [r0], r3
|
|
|
|
vld1.32 {d6[0]}, [r0], r3
|
2014-03-05 09:54:05 +01:00
|
|
|
vld1.32 {d6[1]}, [r0]
|
|
|
|
|
|
|
|
add r0, r2, #1
|
2014-03-04 09:49:34 +01:00
|
|
|
vld1.32 {d7[0]}, [r0], r3
|
|
|
|
vld1.32 {d7[1]}, [r0], r3
|
|
|
|
vld1.32 {d8[0]}, [r0], r3
|
|
|
|
vld1.32 {d8[1]}, [r0]
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vabdl.u8 q15, d0, d2
|
|
|
|
vabdl.u8 q14, d1, d3
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vabdl.u8 q13, d0, d3
|
|
|
|
vabdl.u8 q12, d1, d4
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vabdl.u8 q11, d0, d5
|
|
|
|
vabdl.u8 q10, d1, d6
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vabdl.u8 q9, d0, d7
|
|
|
|
vabdl.u8 q8, d1, d8
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
//Save SAD to 'r4'
|
|
|
|
ldr r0, [sp]
|
|
|
|
vadd.u16 q0, q14, q15
|
|
|
|
vadd.u16 q1, q12, q13
|
|
|
|
vadd.u16 q2, q10, q11
|
|
|
|
vadd.u16 q3, q8 , q9
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vadd.u16 d0, d1
|
|
|
|
vadd.u16 d1, d2, d3
|
|
|
|
vadd.u16 d2, d4, d5
|
|
|
|
vadd.u16 d3, d6, d7
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vpaddl.u16 q0, q0
|
|
|
|
vpaddl.u16 q1, q1
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vpaddl.u32 q0, q0
|
|
|
|
vpaddl.u32 q1, q1
|
2014-03-05 09:54:05 +01:00
|
|
|
|
2014-03-04 09:49:34 +01:00
|
|
|
vst4.32 {d0[0],d1[0],d2[0],d3[0]}, [r0]
|
|
|
|
|
|
|
|
WELS_ASM_FUNC_END
|
|
|
|
|
|
|
|
|
2014-03-05 09:54:05 +01:00
|
|
|
WELS_ASM_FUNC_BEGIN WelsSampleSatd16x16_neon
|
2014-03-04 09:49:34 +01:00
|
|
|
|
|
|
|
SATD_16x4
|
|
|
|
vadd.u16 q15, q0, q2
|
|
|
|
|
|
|
|
SATD_16x4
|
|
|
|
vadd.u16 q15, q15, q0
|
|
|
|
vadd.u16 q15, q15, q2
|
|
|
|
|
|
|
|
SATD_16x4
|
|
|
|
vadd.u16 q15, q15, q0
|
|
|
|
vadd.u16 q15, q15, q2
|
|
|
|
|
|
|
|
SATD_16x4
|
|
|
|
vadd.u16 q15, q15, q0
|
|
|
|
vadd.u16 q15, q15, q2
|
|
|
|
|
|
|
|
vadd.u16 d0, d30, d31
|
|
|
|
vpaddl.u16 d0, d0
|
|
|
|
vpaddl.u32 d0, d0
|
|
|
|
|
|
|
|
vmov.32 r0, d0[0]
|
|
|
|
WELS_ASM_FUNC_END
|
|
|
|
|
|
|
|
|
2014-03-05 09:54:05 +01:00
|
|
|
WELS_ASM_FUNC_BEGIN WelsSampleSatd16x8_neon
|
2014-03-04 09:49:34 +01:00
|
|
|
|
|
|
|
SATD_16x4
|
|
|
|
vadd.u16 q15, q0, q2
|
|
|
|
|
|
|
|
SATD_16x4
|
|
|
|
vadd.u16 q15, q15, q0
|
|
|
|
vadd.u16 q15, q15, q2
|
|
|
|
|
|
|
|
vadd.u16 d0, d30, d31
|
|
|
|
vpaddl.u16 d0, d0
|
|
|
|
vpaddl.u32 d0, d0
|
|
|
|
|
|
|
|
vmov.32 r0, d0[0]
|
|
|
|
WELS_ASM_FUNC_END
|
|
|
|
|
|
|
|
|
2014-03-05 09:54:05 +01:00
|
|
|
WELS_ASM_FUNC_BEGIN WelsSampleSatd8x16_neon
|
2014-03-04 09:49:34 +01:00
|
|
|
|
|
|
|
SATD_8x4
|
|
|
|
vadd.u16 q15, q0, q1
|
|
|
|
|
|
|
|
SATD_8x4
|
|
|
|
vadd.u16 q15, q15, q0
|
|
|
|
vadd.u16 q15, q15, q1
|
|
|
|
|
|
|
|
SATD_8x4
|
|
|
|
vadd.u16 q15, q15, q0
|
|
|
|
vadd.u16 q15, q15, q1
|
|
|
|
|
|
|
|
SATD_8x4
|
|
|
|
vadd.u16 q15, q15, q0
|
|
|
|
vadd.u16 q15, q15, q1
|
|
|
|
|
|
|
|
vadd.u16 d0, d30, d31
|
|
|
|
vpaddl.u16 d0, d0
|
|
|
|
vpaddl.u32 d0, d0
|
|
|
|
|
|
|
|
vmov.32 r0, d0[0]
|
|
|
|
WELS_ASM_FUNC_END
|
|
|
|
|
|
|
|
|
2014-03-05 09:54:05 +01:00
|
|
|
WELS_ASM_FUNC_BEGIN WelsSampleSatd8x8_neon
|
2014-03-04 09:49:34 +01:00
|
|
|
|
|
|
|
SATD_8x4
|
|
|
|
vadd.u16 q15, q0, q1
|
|
|
|
|
|
|
|
SATD_8x4
|
|
|
|
vadd.u16 q15, q15, q0
|
|
|
|
vadd.u16 q15, q15, q1
|
|
|
|
|
|
|
|
vadd.u16 d0, d30, d31
|
|
|
|
vpaddl.u16 d0, d0
|
|
|
|
vpaddl.u32 d0, d0
|
|
|
|
|
|
|
|
vmov.32 r0, d0[0]
|
|
|
|
WELS_ASM_FUNC_END
|
|
|
|
|
|
|
|
|
2014-03-05 09:54:05 +01:00
|
|
|
WELS_ASM_FUNC_BEGIN WelsSampleSatd4x4_neon
|
2014-03-04 09:49:34 +01:00
|
|
|
|
|
|
|
//Load the pix1 data --- 16 bytes
|
|
|
|
vld1.32 {d0[0]}, [r0], r1
|
|
|
|
vld1.32 {d0[1]}, [r0], r1
|
|
|
|
vld1.32 {d1[0]}, [r0], r1
|
|
|
|
vld1.32 {d1[1]}, [r0]
|
|
|
|
|
2014-03-05 09:54:05 +01:00
|
|
|
//Load the pix2 data --- 16 bytes
|
2014-03-04 09:49:34 +01:00
|
|
|
vld1.32 {d2[0]}, [r2], r3
|
|
|
|
vld1.32 {d2[1]}, [r2], r3
|
|
|
|
vld1.32 {d3[0]}, [r2], r3
|
2014-03-05 09:54:05 +01:00
|
|
|
vld1.32 {d3[1]}, [r2]
|
2014-03-04 09:49:34 +01:00
|
|
|
|
|
|
|
//Get the difference
|
|
|
|
vsubl.u8 q15, d0, d2 //{0,1,2,3,4,5,6,7}
|
|
|
|
vsubl.u8 q14, d1, d3 //{8,9,10,11,12,13,14,15}
|
|
|
|
|
|
|
|
//Do the vertical transform
|
|
|
|
vadd.s16 q13, q15, q14 //{0,4,8,12,1,5,9,13}
|
|
|
|
vsub.s16 q12, q15, q14 //{2,6,10,14,3,7,11,15}
|
|
|
|
vswp d27, d24
|
|
|
|
vadd.s16 q15, q13, q12 //{0,1,2,3,4,5,6,7}
|
|
|
|
vsub.s16 q14, q13, q12 //{12,13,14,15,8,9,10,11}
|
|
|
|
|
|
|
|
//Do the horizontal transform
|
|
|
|
vtrn.32 q15, q14
|
|
|
|
vadd.s16 q13, q15, q14
|
|
|
|
vsub.s16 q12, q15, q14
|
|
|
|
|
|
|
|
vtrn.16 q13, q12
|
|
|
|
vadd.s16 q15, q13, q12
|
|
|
|
|
2014-03-05 09:54:05 +01:00
|
|
|
//Do the SAD
|
|
|
|
vabs.s16 q15, q15
|
2014-03-04 09:49:34 +01:00
|
|
|
vabd.s16 q14, q13, q12
|
|
|
|
|
|
|
|
vadd.u16 q0, q15, q14
|
|
|
|
|
|
|
|
vrhadd.u16 d0, d1
|
2014-03-05 09:54:05 +01:00
|
|
|
vpaddl.u16 d0, d0
|
|
|
|
vpaddl.u32 d0, d0
|
2014-03-04 09:49:34 +01:00
|
|
|
|
|
|
|
vmov.u32 r0, d0[0]
|
|
|
|
|
|
|
|
WELS_ASM_FUNC_END
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|