170 lines
5.9 KiB
NASM
170 lines
5.9 KiB
NASM
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;*!
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;* \copy
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;* Copyright (c) 2009-2013, Cisco Systems
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;* All rights reserved.
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;*
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;* Redistribution and use in source and binary forms, with or without
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;* modification, are permitted provided that the following conditions
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;* are met:
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;*
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;* * Redistributions of source code must retain the above copyright
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;* notice, this list of conditions and the following disclaimer.
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;*
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;* * Redistributions in binary form must reproduce the above copyright
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;* notice, this list of conditions and the following disclaimer in
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;* the documentation and/or other materials provided with the
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;* distribution.
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;*
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;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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;* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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;* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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;* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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;* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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;* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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;* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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;* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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;* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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;* POSSIBILITY OF SUCH DAMAGE.
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;*
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;*
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;* cpu_mmx.asm
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;*
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;* Abstract
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;* verify cpuid feature support and cpuid detection
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;*
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;* History
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;* 04/29/2009 Created
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;*
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;*************************************************************************/
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bits 32
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;******************************************************************************************
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; Macros
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;******************************************************************************************
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%macro WELS_EXTERN 1
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%ifdef PREFIX
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global _%1
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%define %1 _%1
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%else
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global %1
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%endif
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%endmacro
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;******************************************************************************************
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; Code
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;******************************************************************************************
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SECTION .text
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; refer to "The IA-32 Intel(R) Architecture Software Developers Manual, Volume 2A A-M"
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; section CPUID - CPU Identification
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WELS_EXTERN WelsCPUIdVerify
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ALIGN 16
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;******************************************************************************************
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; int32_t WelsCPUIdVerify()
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;******************************************************************************************
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WelsCPUIdVerify:
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pushfd ; decrease the SP by 4 and load EFLAGS register onto stack, pushfd 32 bit and pushf for 16 bit
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pushfd ; need push 2 EFLAGS, one for processing and the another one for storing purpose
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pop ecx ; get EFLAGS to bit manipulation
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mov eax, ecx ; store into ecx followed
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xor eax, 00200000h ; get ID flag (bit 21) of EFLAGS to directly indicate cpuid support or not
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xor eax, ecx ; get the ID flag bitwise, eax - 0: not support; otherwise: support
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popfd ; store back EFLAGS and keep unchanged for system
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ret
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WELS_EXTERN WelsCPUId
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ALIGN 16
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;****************************************************************************************************
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; void WelsCPUId( int32_t uiIndex, int32_t *pFeatureA, int32_t *pFeatureB, int32_t *pFeatureC, int32_t *pFeatureD )
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;****************************************************************************************************
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WelsCPUId:
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push ebx
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push edi
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mov eax, [esp+12] ; operating index
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cpuid ; cpuid
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; processing various information return
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mov edi, [esp+16]
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mov [edi], eax
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mov edi, [esp+20]
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mov [edi], ebx
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mov edi, [esp+24]
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mov [edi], ecx
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mov edi, [esp+28]
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mov [edi], edx
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pop edi
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pop ebx
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ret
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WELS_EXTERN WelsCPUSupportAVX
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; need call after cpuid=1 and eax, ecx flag got then
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ALIGN 16
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;****************************************************************************************************
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; int32_t WelsCPUSupportAVX( uint32_t eax, uint32_t ecx )
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;****************************************************************************************************
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WelsCPUSupportAVX:
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mov eax, [esp+4]
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mov ecx, [esp+8]
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; refer to detection of AVX addressed in INTEL AVX manual document
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and ecx, 018000000H
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cmp ecx, 018000000H ; check both OSXSAVE and AVX feature flags
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jne avx_not_supported
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; processor supports AVX instructions and XGETBV is enabled by OS
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mov ecx, 0 ; specify 0 for XFEATURE_ENABLED_MASK register
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XGETBV ; result in EDX:EAX
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and eax, 06H
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cmp eax, 06H ; check OS has enabled both XMM and YMM state support
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jne avx_not_supported
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mov eax, 1
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ret
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avx_not_supported:
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mov eax, 0
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ret
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WELS_EXTERN WelsCPUSupportFMA
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; need call after cpuid=1 and eax, ecx flag got then
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ALIGN 16
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;****************************************************************************************************
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; int32_t WelsCPUSupportFMA( uint32_t eax, uint32_t ecx )
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;****************************************************************************************************
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WelsCPUSupportFMA:
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mov eax, [esp+4]
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mov ecx, [esp+8]
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; refer to detection of FMA addressed in INTEL AVX manual document
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and ecx, 018001000H
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cmp ecx, 018001000H ; check OSXSAVE, AVX, FMA feature flags
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jne fma_not_supported
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; processor supports AVX,FMA instructions and XGETBV is enabled by OS
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mov ecx, 0 ; specify 0 for XFEATURE_ENABLED_MASK register
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XGETBV ; result in EDX:EAX
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and eax, 06H
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cmp eax, 06H ; check OS has enabled both XMM and YMM state support
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jne fma_not_supported
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mov eax, 1
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ret
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fma_not_supported:
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mov eax, 0
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ret
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WELS_EXTERN WelsEmms
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ALIGN 16
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;******************************************************************************************
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; void WelsEmms()
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;******************************************************************************************
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WelsEmms:
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emms ; empty mmx technology states
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ret
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