212 lines
6.2 KiB
C++
212 lines
6.2 KiB
C++
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/*!
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* \copy
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* Copyright (c) 2009-2013, Cisco Systems
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*
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* \file cpu.cpp
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*
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* \brief CPU compatibility detection
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*
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* \date 04/29/2009 Created
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*
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*************************************************************************************
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*/
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#include <string.h>
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#include "cpu.h"
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#include "cpu_core.h"
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namespace WelsDec {
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#define CPU_Vender_AMD "AuthenticAMD"
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#define CPU_Vender_INTEL "GenuineIntel"
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#define CPU_Vender_CYRIX "CyrixInstead"
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#if defined(X86_ASM)
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uint32_t WelsCPUFeatureDetect( int32_t *pNumberOfLogicProcessors )
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{
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uint32_t uiCPU = 0;
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uint32_t uiFeatureA = 0, uiFeatureB = 0, uiFeatureC = 0, uiFeatureD = 0;
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int32_t CacheLineSize = 0;
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int8_t chVenderName[16] = { 0 };
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if( !WelsCPUIdVerify() )
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{
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/* cpuid is not supported in cpu */
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return 0;
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}
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WelsCPUId( 0, &uiFeatureA, (uint32_t*)&chVenderName[0],(uint32_t*)&chVenderName[8],(uint32_t*)&chVenderName[4] );
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if( uiFeatureA == 0 )
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{
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/* maximum input value for basic cpuid information */
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return 0;
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}
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WelsCPUId( 1, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD );
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if( (uiFeatureD & 0x00800000) == 0 )
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{
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/* Basic MMX technology is not support in cpu, mean nothing for us so return here */
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return 0;
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}
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uiCPU = WELS_CPU_MMX;
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if( uiFeatureD & 0x02000000 )
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{
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/* SSE technology is identical to AMD MMX extensions */
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uiCPU |= WELS_CPU_MMXEXT|WELS_CPU_SSE;
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}
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if( uiFeatureD & 0x04000000 )
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{
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/* SSE2 support here */
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uiCPU |= WELS_CPU_SSE2;
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}
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if ( uiFeatureD & 0x00000001 )
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{
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/* x87 FPU on-chip checking */
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uiCPU |= WELS_CPU_FPU;
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}
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if ( uiFeatureD & 0x00008000 )
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{
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/* CMOV instruction checking */
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uiCPU |= WELS_CPU_CMOV;
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}
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if ( !strcmp((const str_t*)chVenderName,CPU_Vender_INTEL) ) // confirmed_safe_unsafe_usage
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{
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if ( uiFeatureD & 0x10000000 )
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{
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/* Multi-Threading checking: contains of multiple logic processors */
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uiCPU |= WELS_CPU_HTT;
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}
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}
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if( uiFeatureC & 0x00000001 ){
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/* SSE3 support here */
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uiCPU |= WELS_CPU_SSE3;
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}
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if( uiFeatureC & 0x00000200 ){
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/* SSSE3 support here */
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uiCPU |= WELS_CPU_SSSE3;
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}
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if( uiFeatureC & 0x00080000 ){
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/* SSE4.1 support here, 45nm Penryn processor */
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uiCPU |= WELS_CPU_SSE41;
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}
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if( uiFeatureC & 0x00100000 ){
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/* SSE4.2 support here, next generation Nehalem processor */
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uiCPU |= WELS_CPU_SSE42;
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}
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if ( WelsCPUSupportAVX( uiFeatureA, uiFeatureC ) )
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{
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/* AVX supported */
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uiCPU |= WELS_CPU_AVX;
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}
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if ( WelsCPUSupportFMA( uiFeatureA, uiFeatureC ) )
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{
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/* AVX FMA supported */
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uiCPU |= WELS_CPU_FMA;
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}
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if ( uiFeatureC & 0x02000000 )
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{
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/* AES checking */
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uiCPU |= WELS_CPU_AES;
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}
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if ( uiFeatureC & 0x00400000 )
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{
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/* MOVBE checking */
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uiCPU |= WELS_CPU_MOVBE;
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}
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if ( pNumberOfLogicProcessors != NULL )
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{
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// HTT enabled on chip
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*pNumberOfLogicProcessors = (uiFeatureB & 0x00ff0000) >> 16; // feature bits: 23-16 on returned EBX
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}
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WelsCPUId( 0x80000000, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD );
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if( (!strcmp((const str_t*)chVenderName,CPU_Vender_AMD)) && (uiFeatureA>=0x80000001) ){ // confirmed_safe_unsafe_usage
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WelsCPUId(0x80000001, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD );
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if( uiFeatureD&0x00400000 ){
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uiCPU |= WELS_CPU_MMXEXT;
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}
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if( uiFeatureD&0x80000000 ){
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uiCPU |= WELS_CPU_3DNOW;
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}
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}
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if( !strcmp((const str_t*)chVenderName,CPU_Vender_INTEL) ){ // confirmed_safe_unsafe_usage
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int32_t family, model;
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WelsCPUId(1, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD);
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family = ((uiFeatureA>>8)&0xf) + ((uiFeatureA>>20)&0xff);
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model = ((uiFeatureA>>4)&0xf) + ((uiFeatureA>>12)&0xf0);
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if( (family==6) && (model==9 || model==13 || model==14) ){
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uiCPU &= ~(WELS_CPU_SSE2|WELS_CPU_SSE3);
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}
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}
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// get cache line size
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if( (!strcmp((const str_t*)chVenderName,CPU_Vender_INTEL)) || !(strcmp((const str_t*)chVenderName,CPU_Vender_CYRIX)) ){ // confirmed_safe_unsafe_usage
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WelsCPUId(1, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD);
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CacheLineSize = (uiFeatureB&0xff00)>>5; // ((clflush_line_size >> 8) << 3), CLFLUSH_line_size * 8 = CacheLineSize_in_byte
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if( CacheLineSize == 128 ){
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uiCPU |= WELS_CPU_CACHELINE_128;
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}
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else if( CacheLineSize == 64 ){
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uiCPU |= WELS_CPU_CACHELINE_64;
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}
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else if( CacheLineSize == 32 ){
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uiCPU |= WELS_CPU_CACHELINE_32;
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}
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else if( CacheLineSize == 16 ){
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uiCPU |= WELS_CPU_CACHELINE_16;
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}
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}
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return uiCPU;
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}
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void WelsCPURestore( const uint32_t kuiCPU )
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{
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if( kuiCPU & (WELS_CPU_MMX|WELS_CPU_MMXEXT|WELS_CPU_3DNOW|WELS_CPU_3DNOWEXT) )
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{
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WelsEmms();
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}
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}
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#endif
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} // namespace WelsDec
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