253 lines
8.5 KiB
C
253 lines
8.5 KiB
C
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/*!
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* \copy
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* Copyright (c) 2013, Cisco Systems
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef WELS_VIDEO_CODEC_DEFINITION_H__
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#define WELS_VIDEO_CODEC_DEFINITION_H__
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#if defined(WIN32)
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#pragma once
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#endif//WIN32
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typedef enum
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{
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/*rgb color formats*/
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videoFormatRGB = 1,
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videoFormatRGBA = 2,
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videoFormatRGB555 = 3,
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videoFormatRGB565 = 4,
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videoFormatBGR = 5,
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videoFormatBGRA = 6,
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videoFormatABGR = 7,
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videoFormatARGB = 8,
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/*yuv color formats*/
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videoFormatYUY2 = 20,
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videoFormatYVYU = 21,
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videoFormatUYVY = 22,
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videoFormatI420 = 23, //same as IYUV
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videoFormatYV12 = 24,
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videoFormatInternal = 25, // Only Used for SVC decoder testbed
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videoFormatNV12 = 26, // new format for output by DXVA decoding
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videoFormatVFlip = 0x80000000
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}EVideoFormatType;
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typedef enum
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{
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videoFrameTypeInvalid, /* Encoder not ready or parameters are invalidate */
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videoFrameTypeIDR, /* This type is only available for H264 if this frame is key frame, then return this type */
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videoFrameTypeI, /* I frame type */
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videoFrameTypeP, /* P frame type */
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videoFrameTypeSkip, /* Skip the frame based encoder kernel */
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videoFrameTypeIPMixed, /* Frame type introduced I and P slices are mixing */
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}EVideoFrameType;
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typedef enum
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{
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cmResultSuccess,
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cmInitParaError, /*Parameters are invalid */
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cmMachPerfIsBad, /*The performance of machine is not enough to support
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H264 CODEC, in this case, suggestion user use h263
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or set fps to low like 5fps or more low*/
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cmUnkonwReason,
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cmMallocMemeError, /*Malloc a memory error*/
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cmInitExpected, /*Initial action is expected*/
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}CM_RETURN;
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/* nal unit type */
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enum ENalUnitType
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{
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NAL_UNKNOWN = 0,
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NAL_SLICE = 1,
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NAL_SLICE_DPA = 2,
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NAL_SLICE_DPB = 3,
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NAL_SLICE_DPC = 4,
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NAL_SLICE_IDR = 5, /* ref_idc != 0 */
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NAL_SEI = 6, /* ref_idc == 0 */
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NAL_SPS = 7,
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NAL_PPS = 8
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/* ref_idc == 0 for 6,9,10,11,12 */
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};
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/* NRI: eNalRefIdc */
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enum ENalPriority
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{
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NAL_PRIORITY_DISPOSABLE = 0,
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NAL_PRIORITY_LOW = 1,
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NAL_PRIORITY_HIGH = 2,
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NAL_PRIORITY_HIGHEST = 3,
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};
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#define IS_PARAMETER_SET_NAL(eNalRefIdc, eNalType) \
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( (eNalRefIdc == NAL_PRIORITY_HIGHEST) && (eNalType == (NAL_SPS|NAL_PPS) || eNalType == NAL_SPS) )
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#define IS_IDR_NAL(eNalRefIdc, eNalType) \
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( (eNalRefIdc == NAL_PRIORITY_HIGHEST) && (eNalType == NAL_SLICE_IDR) )
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#define FRAME_NUM_PARAM_SET (-1)
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#define FRAME_NUM_IDR 0
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#pragma pack(1)
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/* Error Tools definition */
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typedef unsigned short ERR_TOOL;
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enum{
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ET_NONE = 0x00, // NONE Error Tools
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ET_IP_SCALE = 0x01, // IP Scalable
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ET_FMO = 0x02, // Flexible Macroblock Ordering
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ET_IR_R1 = 0x04, // Intra Refresh in predifined 2% MB
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ET_IR_R2 = 0x08, // Intra Refresh in predifined 5% MB
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ET_IR_R3 = 0x10, // Intra Refresh in predifined 10% MB
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ET_FEC_HALF = 0x20, // Forward Error Correction in 50% redundency mode
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ET_FEC_FULL = 0x40, // Forward Error Correction in 100% redundency mode
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ET_RFS = 0x80, // Reference Frame Selection
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};
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/* information of coded Slice(=NAL)(s) */
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typedef struct SliceInformation
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{
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unsigned char* pBufferOfSlices; // base buffer of coded slice(s)
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int iCodedSliceCount; // number of coded slices
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unsigned int* pLengthOfSlices; // array of slices length accordingly by number of slice
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int iFecType; // FEC type[0, 50%FEC, 100%FEC]
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unsigned char uiSliceIdx; // index of slice in frame [FMO: 0,..,uiSliceCount-1; No FMO: 0]
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unsigned char uiSliceCount; // count number of slice in frame [FMO: 2-8; No FMO: 1]
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char iFrameIndex; // index of frame[-1, .., idr_interval-1]
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unsigned char uiNalRefIdc; // NRI, priority level of slice(NAL)
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unsigned char uiNalType; // NAL type
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unsigned char uiContainingFinalNal; // whether final NAL is involved in buffer of coded slices, flag used in Pause feature in T27
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} SliceInfo, *PSliceInfo;
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#define CIF_WIDTH 352
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#define CIF_HEIGHT 288
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#define QVGA_WIDTH 320
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#define QVGA_HEIGHT 240
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#define QCIF_WIDTH 176
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#define QCIF_HEIGHT 144
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#define SQCIF_WIDTH 128
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#define SQCIF_HEIGHT 96
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/* thresholds of the initial, maximal and minimal rate */
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typedef struct {
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int iWidth; // frame width
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int iHeight; // frame height
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int iThresholdOfInitRate; // threshold of initial rate
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int iThresholdOfMaxRate; // threshold of maximal rate
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int iThresholdOfMinRate; // threshold of minimal rate
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int iMinThresholdFrameRate; //min frame rate min
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int iSkipFrameRate; //skip to frame rate min
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int iSkipFrameStep; //how many frames to skip
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}SRateThresholds, *PRateThresholds;
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/*new interface*/
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typedef struct WelsDeviceInfo
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{
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int bSupport; /* a logic flag provided by decoder which indicates whether GPU decoder can work based on the following device info. */
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char Vendor[128]; // vendor name
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char Device[128]; // device name
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char Driver[128]; // driver version
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char DriverDate[128]; // driver release date
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} Device_Info;
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typedef enum TagBufferProperty
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{
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BUFFER_HOST = 0, // host memory
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BUFFER_DEVICE = 1, // device memory including surface and shared handle
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// for DXVA: shared handle
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// for VDA : iosurface
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//SURFACE_DEVICE , // surface
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//SHARED_HANDLE // shared handle
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}EBufferProperty;
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typedef enum TagDecodeMode
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{
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AUTO_MODE = 0, // decided by decoder itself, dynamic mode switch, delayed switch
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SW_MODE = 1, // decoded by CPU, instant switch
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GPU_MODE = 2, // decoded by GPU, instant switch
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SWITCH_MODE =3 // switch to the other mode, forced mode switch, delayed switch
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}EDecodeMode;
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typedef struct TagSysMemBuffer
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{
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int iWidth; //width of decoded pic for display
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int iHeight; //height of decoded pic for display
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int iFormat; // type is "EVideoFormatType"
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int iStride[2]; //stride of 2 component
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}SSysMEMBuffer;
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typedef struct TagVideoMemBuffer
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{
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int iSurfaceWidth; // used for surface create
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int iSurfaceHeight;
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int D3Dformat; //type is "D3DFORMAT"
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int D3DPool; // type is "D3DPOOL";
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int iLeftTopX;
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int iLeftTopY;
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int iRightBottomX;
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int iRightBottomY;
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}SVideoMemBuffer;
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typedef struct TagBufferInfo
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{
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EBufferProperty eBufferProperty; //0: host memory; 1: device memory;
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int iBufferStatus; // 0: one frame data is not ready; 1: one frame data is ready
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EDecodeMode eWorkMode; //indicate what the real working mode in decoder
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union {
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SSysMEMBuffer sSystemBuffer;
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SVideoMemBuffer sVideoBuffer;
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}UsrData;
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}SBufferInfo;
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/* Constants related to transmission rate at various resolutions */
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static const SRateThresholds ksRateThrMap[4] = {
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// initial-maximal-minimal
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{CIF_WIDTH, CIF_HEIGHT, 225000, 384000, 96000, 3, 1, 1}, // CIF
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{QVGA_WIDTH, QVGA_HEIGHT, 192000, 320000, 80000, -1, -1, -1}, // QVGA
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{QCIF_WIDTH, QCIF_HEIGHT, 150000, 256000, 64000, 8, 4, 2}, // QCIF
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{SQCIF_WIDTH, SQCIF_HEIGHT, 120000, 192000, 48000, 5, 3, 1} // SQCIF
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};
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// In a GOP, multiple of the key frame number, derived from
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// the number of layers(index or array below)
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static const char kiKeyNumMultiple[] = {
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1, 1, 2, 4, 8, 16,
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};
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#pragma pack()
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#endif//WELS_VIDEO_CODEC_DEFINITION_H__
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