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5f45f3f310
Change-Id: I9b8932eb02ed6bc44756f6505e7efbfad1706b46 Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>
179 lines
4.6 KiB
ArmAsm
179 lines
4.6 KiB
ArmAsm
/**********************************************************************
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Copyright(c) 2019 Arm Corporation All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Arm Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**********************************************************************/
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.arch armv8-a+crypto
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.text
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.align 3
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/*
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Macros
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*/
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.macro declare_var_vector_reg name:req,reg:req
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\name\()_q .req q\reg
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\name\()_v .req v\reg
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\name\()_s .req s\reg
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\name\()_d .req d\reg
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.endm
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.macro mod_adler dest:req,tmp:req
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umull \tmp\()_x,\dest,const_div1
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lsr \tmp\()_x,\tmp\()_x,47
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msub \dest,\tmp,const_div2,\dest
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.endm
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/*
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uint32_t adler32_neon(uint32_t adler32, uint8_t * start, uint32_t length);
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*/
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/*
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Arguements list
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*/
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adler32 .req w0
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start .req x1
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length .req x2
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.global adler32_neon
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.type adler32_neon, %function
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adler32_neon:
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/*
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local variables
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*/
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declare_var_vector_reg factor0 , 6
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declare_var_vector_reg factor1 , 7
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declare_var_vector_reg d0 , 4
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declare_var_vector_reg d1 , 5
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declare_var_vector_reg adacc , 2
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declare_var_vector_reg s2acc , 3
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declare_var_vector_reg zero , 16
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declare_var_vector_reg adler , 17
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declare_var_vector_reg back_d0 , 18
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declare_var_vector_reg back_d1 , 19
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declare_var_vector_reg sum2 , 20
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declare_var_vector_reg tmp2 , 20
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adler0 .req w4
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adler1 .req w5
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adler0_x .req x4
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adler1_x .req x5
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end .req x0
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tmp .req w8
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tmp_x .req x8
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tmp1_x .req x9
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loop_cnt .req x10
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loop_const .req x11
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const_div1 .req w6
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const_div2 .req w7
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mov const_div1, 32881
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movk const_div1, 0x8007, lsl 16
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mov const_div2, 65521
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and adler0, adler32, 0xffff
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lsr adler1, adler32, 16
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lsr loop_cnt,length,5
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adrp x3,factors
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add x3,x3,:lo12:factors
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ld1 {factor0_v.16b-factor1_v.16b},[x3]
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add end,start,length
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cbz loop_cnt,final_accum32
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ld1 {back_d0_v.16b-back_d1_v.16b},[start]
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mov loop_const,173
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movi v16.4s,0
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great_than_32:
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cmp loop_cnt,173
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csel loop_const,loop_cnt,loop_const,le
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mov adacc_v.16b,zero_v.16b
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mov s2acc_v.16b,zero_v.16b
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ins adacc_v.s[0],adler0
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ins s2acc_v.s[0],adler1
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add tmp_x,start,loop_const,lsl 5
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accum32_neon:
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add start,start,32
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mov d0_v.16b,back_d0_v.16b
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mov d1_v.16b,back_d1_v.16b
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ld1 {back_d0_v.16b-back_d1_v.16b},[start]
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shl tmp2_v.4s,adacc_v.4s,5
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add s2acc_v.4s,s2acc_v.4s,tmp2_v.4s
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uaddlp adler_v.8h,d0_v.16b
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uadalp adler_v.8h,d1_v.16b
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uadalp adacc_v.4s,adler_v.8h
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umull sum2_v.8h,factor0_v.8b ,d0_v.8b
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umlal2 sum2_v.8h,factor0_v.16b,d0_v.16b
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umlal sum2_v.8h,factor1_v.8b ,d1_v.8b
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umlal2 sum2_v.8h,factor1_v.16b,d1_v.16b
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uadalp s2acc_v.4s,sum2_v.8h
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cmp start,tmp_x
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bne accum32_neon
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uaddlv adacc_d,adacc_v.4s
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uaddlv s2acc_d,s2acc_v.4s
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fmov adler0_x,adacc_d
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fmov adler1_x,s2acc_d
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mod_adler adler0,tmp
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mod_adler adler1,tmp
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sub loop_cnt,loop_cnt,loop_const
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cbnz loop_cnt,great_than_32
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final_accum32:
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and length,length,31
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cbz length,end_func
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accum32_body:
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cmp start,end
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beq end_func
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ldrb tmp,[start],1
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add adler0,adler0,tmp
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add adler1,adler1,adler0
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b accum32_body
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end_func:
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mod_adler adler0,tmp
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mod_adler adler1,tmp
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orr w0,adler0,adler1,lsl 16
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ret
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.size adler32_neon, .-adler32_neon
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.section .rodata.cst16,"aM",@progbits,16
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.align 4
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factors:
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.quad 0x191a1b1c1d1e1f20
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.quad 0x1112131415161718
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.quad 0x090a0b0c0d0e0f10
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.quad 0x0102030405060708
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