isa-l/isa-l.def
Greg Tucker d6c5e9620d Add raid unit
New raid unit adds source for optimized xor and P+Q functions.

Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
2016-04-26 15:58:49 -07:00

72 lines
1.9 KiB
Modula-2

LIBRARY isa-l
EXPORTS
ec_encode_data_sse @1
ec_init_tables @2
gf_gen_cauchy1_matrix @3
gf_gen_rs_matrix @4
gf_invert_matrix @5
gf_mul @6
gf_vect_dot_prod_base @7
gf_vect_mul_base @8
ec_encode_data_base @9
gf_vect_mul_init @10
gf_vect_mul_sse @11
gf_vect_mul_avx @12
gf_vect_dot_prod_sse @13
gf_vect_dot_prod_avx @14
gf_vect_dot_prod_avx2 @15
gf_2vect_dot_prod_sse @16
gf_3vect_dot_prod_sse @17
gf_4vect_dot_prod_sse @18
gf_5vect_dot_prod_sse @19
gf_6vect_dot_prod_sse @20
gf_2vect_dot_prod_avx @21
gf_3vect_dot_prod_avx @22
gf_4vect_dot_prod_avx @23
gf_5vect_dot_prod_avx @24
gf_6vect_dot_prod_avx @25
gf_2vect_dot_prod_avx2 @26
gf_3vect_dot_prod_avx2 @27
gf_4vect_dot_prod_avx2 @28
gf_5vect_dot_prod_avx2 @29
gf_6vect_dot_prod_avx2 @30
gf_vect_mad_sse @31
gf_2vect_mad_sse @32
gf_3vect_mad_sse @33
gf_4vect_mad_sse @34
gf_5vect_mad_sse @35
gf_6vect_mad_sse @36
gf_vect_mad_avx @37
gf_2vect_mad_avx @38
gf_3vect_mad_avx @39
gf_4vect_mad_avx @40
gf_5vect_mad_avx @41
gf_6vect_mad_avx @42
gf_vect_mad_avx2 @43
gf_2vect_mad_avx2 @44
gf_3vect_mad_avx2 @45
gf_4vect_mad_avx2 @46
gf_5vect_mad_avx2 @47
gf_6vect_mad_avx2 @48
ec_encode_data @49
gf_vect_mul @50
ec_encode_data_update @51
gf_vect_dot_prod @52
gf_vect_mad @53
xor_gen @54
xor_check @55
pq_gen @56
pq_check @57
xor_gen_sse @58
xor_gen_avx @59
xor_check_sse @60
pq_gen_sse @61
pq_gen_avx @62
pq_gen_avx2 @63
pq_check_sse @64
pq_gen_base @65
xor_gen_base @66
xor_check_base @67
pq_check_base @68