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cd888f01a4
To support Intel CET, all indirect branch targets must start with ENDBR32/ENDBR64. Here is a patch to define endbranch and add it to function entries in x86 assembly codes which are indirect branch targets as discovered by running testsuite on Intel CET machine and visual inspection. Verified with $ CC="gcc -Wl,-z,cet-report=error -fcf-protection" CXX="g++ -Wl,-z,cet-report=error -fcf-protection" .../configure x86_64-linux $ make -j8 $ make -j8 check with both nasm and yasm on both CET and non-CET machines. Change-Id: I9822578e7294fb5043a64ab7de5c41de81a7d337 Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
272 lines
6.0 KiB
NASM
272 lines
6.0 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; gf_vect_dot_prod_avx(len, vec, *g_tbls, **buffs, *dest);
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;;;
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%include "reg_sizes.asm"
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%ifidn __OUTPUT_FORMAT__, elf64
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%define arg0 rdi
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%define arg1 rsi
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%define arg2 rdx
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%define arg3 rcx
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%define arg4 r8
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%define tmp r11
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%define tmp2 r10
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%define tmp3 r9
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%define return rax
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%macro SLDR 2
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%endmacro
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%define SSTR SLDR
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%define PS 8
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%define func(x) x: endbranch
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%define FUNC_SAVE
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%define FUNC_RESTORE
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%endif
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%ifidn __OUTPUT_FORMAT__, win64
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%define arg0 rcx
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%define arg1 rdx
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%define arg2 r8
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%define arg3 r9
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%define arg4 r12 ; must be saved and loaded
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%define tmp r11
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%define tmp2 r10
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%define tmp3 rdi ; must be saved and loaded
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%define return rax
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%macro SLDR 2
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%endmacro
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%define SSTR SLDR
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%define PS 8
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%define frame_size 2*8
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%define arg(x) [rsp + frame_size + PS + PS*x]
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%define func(x) proc_frame x
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%macro FUNC_SAVE 0
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rex_push_reg r12
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push_reg rdi
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end_prolog
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mov arg4, arg(4)
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%endmacro
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%macro FUNC_RESTORE 0
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pop rdi
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pop r12
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%endmacro
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%endif
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%ifidn __OUTPUT_FORMAT__, elf32
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;;;================== High Address;
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;;; arg4
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;;; arg3
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;;; arg2
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;;; arg1
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;;; arg0
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;;; return
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;;;<================= esp of caller
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;;; ebp
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;;;<================= ebp = esp
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;;; esi
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;;; edi
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;;; ebx
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;;;<================= esp of callee
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;;;
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;;;================== Low Address;
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%define PS 4
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%define LOG_PS 2
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%define func(x) x: endbranch
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%define arg(x) [ebp + PS*2 + PS*x]
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%define trans ecx ;trans is for the variables in stack
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%define arg0 trans
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%define arg0_m arg(0)
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%define arg1 trans
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%define arg1_m arg(1)
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%define arg2 arg2_m
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%define arg2_m arg(2)
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%define arg3 ebx
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%define arg4 trans
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%define arg4_m arg(4)
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%define tmp edx
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%define tmp2 edi
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%define tmp3 esi
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%define return eax
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%macro SLDR 2 ;; stack load/restore
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mov %1, %2
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%endmacro
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%define SSTR SLDR
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%macro FUNC_SAVE 0
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push ebp
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mov ebp, esp
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push esi
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push edi
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push ebx
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mov arg3, arg(3)
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%endmacro
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%macro FUNC_RESTORE 0
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pop ebx
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pop edi
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pop esi
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mov esp, ebp
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pop ebp
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%endmacro
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%endif ; output formats
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%define len arg0
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%define vec arg1
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%define mul_array arg2
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%define src arg3
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%define dest arg4
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%define vec_i tmp2
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%define ptr tmp3
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%define pos return
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%ifidn PS,4 ;32-bit code
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%define vec_m arg1_m
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%define len_m arg0_m
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%define dest_m arg4_m
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%endif
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%ifndef EC_ALIGNED_ADDR
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;;; Use Un-aligned load/store
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%define XLDR vmovdqu
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%define XSTR vmovdqu
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%else
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;;; Use Non-temporal load/stor
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%ifdef NO_NT_LDST
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%define XLDR vmovdqa
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%define XSTR vmovdqa
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%else
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%define XLDR vmovntdqa
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%define XSTR vmovntdq
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%endif
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%endif
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%ifidn PS,8 ; 64-bit code
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default rel
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[bits 64]
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%endif
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section .text
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%define xmask0f xmm5
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%define xgft_lo xmm4
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%define xgft_hi xmm3
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%define x0 xmm0
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%define xtmpa xmm1
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%define xp xmm2
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align 16
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mk_global gf_vect_dot_prod_avx, function
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func(gf_vect_dot_prod_avx)
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FUNC_SAVE
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SLDR len, len_m
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sub len, 16
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SSTR len_m, len
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jl .return_fail
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xor pos, pos
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vmovdqa xmask0f, [mask0f] ;Load mask of lower nibble in each byte
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.loop16:
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vpxor xp, xp
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mov tmp, mul_array
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xor vec_i, vec_i
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.next_vect:
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mov ptr, [src+vec_i*PS]
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vmovdqu xgft_lo, [tmp] ;Load array Cx{00}, Cx{01}, ..., Cx{0f}
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vmovdqu xgft_hi, [tmp+16] ; " Cx{00}, Cx{10}, ..., Cx{f0}
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XLDR x0, [ptr+pos] ;Get next source vector
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add tmp, 32
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add vec_i, 1
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vpand xtmpa, x0, xmask0f ;Mask low src nibble in bits 4-0
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vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
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vpand x0, x0, xmask0f ;Mask high src nibble in bits 4-0
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vpshufb xgft_hi, xgft_hi, x0 ;Lookup mul table of high nibble
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vpshufb xgft_lo, xgft_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xgft_hi, xgft_hi, xgft_lo ;GF add high and low partials
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vpxor xp, xp, xgft_hi ;xp += partial
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SLDR vec, vec_m
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cmp vec_i, vec
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jl .next_vect
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SLDR dest, dest_m
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XSTR [dest+pos], xp
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add pos, 16 ;Loop on 16 bytes at a time
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SLDR len, len_m
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cmp pos, len
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jle .loop16
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lea tmp, [len + 16]
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cmp pos, tmp
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je .return_pass
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;; Tail len
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mov pos, len ;Overlapped offset length-16
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jmp .loop16 ;Do one more overlap pass
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.return_pass:
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mov return, 0
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FUNC_RESTORE
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ret
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.return_fail:
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mov return, 1
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FUNC_RESTORE
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ret
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endproc_frame
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section .data
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align 16
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mask0f:
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dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
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;;; func core, ver, snum
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slversion gf_vect_dot_prod_avx, 02, 05, 0061
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