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cd888f01a4
To support Intel CET, all indirect branch targets must start with ENDBR32/ENDBR64. Here is a patch to define endbranch and add it to function entries in x86 assembly codes which are indirect branch targets as discovered by running testsuite on Intel CET machine and visual inspection. Verified with $ CC="gcc -Wl,-z,cet-report=error -fcf-protection" CXX="g++ -Wl,-z,cet-report=error -fcf-protection" .../configure x86_64-linux $ make -j8 $ make -j8 check with both nasm and yasm on both CET and non-CET machines. Change-Id: I9822578e7294fb5043a64ab7de5c41de81a7d337 Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
283 lines
7.6 KiB
NASM
283 lines
7.6 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;; Optimized pq of N source vectors using SSE3
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;;; int pq_gen_sse(int vects, int len, void **array)
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;;; Generates P+Q parity vector from N (vects-2) sources in array of pointers
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;;; (**array). Last two pointers are the P and Q destinations respectively.
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;;; Vectors must be aligned to 16 bytes. Length must be 16 byte aligned.
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%include "reg_sizes.asm"
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%ifidn __OUTPUT_FORMAT__, elf64
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%define arg0 rdi
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%define arg1 rsi
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%define arg2 rdx
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%define arg3 rcx
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%define arg4 r8
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%define arg5 r9
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%define tmp r11
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%define return rax
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%define PS 8
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%define func(x) x: endbranch
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%define FUNC_SAVE
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%define FUNC_RESTORE
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%elifidn __OUTPUT_FORMAT__, win64
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%define arg0 rcx
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%define arg1 rdx
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%define arg2 r8
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%define arg3 r9
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%define return rax
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%define PS 8
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%define tmp r11
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%define stack_size 2*16 + 8 ; must be an odd multiple of 8
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%define func(x) proc_frame x
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%macro FUNC_SAVE 0
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alloc_stack stack_size
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save_xmm128 xmm6, 0*16
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save_xmm128 xmm7, 1*16
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end_prolog
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%endmacro
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%macro FUNC_RESTORE 0
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movdqa xmm6, [rsp + 0*16]
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movdqa xmm7, [rsp + 1*16]
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add rsp, stack_size
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%endmacro
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%elifidn __OUTPUT_FORMAT__, elf32
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%define arg0 edx
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%define arg1 ecx
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%define return eax
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%define PS 4
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%define func(x) x: endbranch
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%define arg(x) [ebp+8+PS*x]
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%define arg2 edi ; must sav/restore
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%define arg3 esi
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%define tmp ebx
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%macro FUNC_SAVE 0
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push ebp
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mov ebp, esp
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push esi
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push edi
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push ebx
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mov arg0, arg(0)
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mov arg1, arg(1)
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mov arg2, arg(2)
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%endmacro
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%macro FUNC_RESTORE 0
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pop ebx
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pop edi
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pop esi
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mov esp, ebp ;if has frame pointer?
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pop ebp
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%endmacro
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%endif ; output formats
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%define vec arg0
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%define len arg1
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%define ptr arg3
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%define pos return
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%define xp1 xmm0
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%define xq1 xmm1
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%define xtmp1 xmm2
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%define xs1 xmm3
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%define xp2 xmm4
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%define xq2 xmm5
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%define xtmp2 xmm6
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%define xs2 xmm7
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%ifidn PS,8 ; 64-bit code
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default rel
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[bits 64]
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%define xpoly xmm15
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%elifidn PS,4 ; 32-bit code
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%define xpoly [poly]
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%endif
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;;; Use Non-temporal load/stor
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%ifdef NO_NT_LDST
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%define XLDR movdqa
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%define XSTR movdqa
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%else
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%define XLDR movntdqa
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%define XSTR movntdq
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%endif
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section .text
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align 16
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mk_global pq_check_sse, function
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func(pq_check_sse)
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FUNC_SAVE
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sub vec, 3 ;Keep as offset to last source
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jng return_fail ;Must have at least 2 sources
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cmp len, 0
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je return_pass
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test len, (16-1) ;Check alignment of length
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jnz return_fail
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mov pos, 0
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%ifidn PS,8
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movdqa xpoly, [poly] ;For 64-bit, load poly into high xmm reg
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%endif
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cmp len, 32
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jl loop16
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len_aligned_32bytes:
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sub len, 32 ;Do end of vec first and run backward
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loop32:
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mov ptr, [arg2+PS+vec*PS] ;Get address of P parity vector
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mov tmp, [arg2+(2*PS)+vec*PS] ;Get address of Q parity vector
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XLDR xp1, [ptr+pos] ;Initialize xp1 with P1 src
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XLDR xp2, [ptr+pos+16] ;Initialize xp2 with P2 src + 16B ahead
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pxor xq1, xq1 ;q1 = 0
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pxor xq2, xq2 ;q2 = 0
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mov ptr, [arg2+vec*PS] ;Fetch last source pointer
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mov tmp, vec ;Set tmp to point back to last vector
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XLDR xs1, [ptr+pos] ;Preload last vector (source)
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XLDR xs2, [ptr+pos+16] ;Preload last vector (source)
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next_vect:
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sub tmp, 1 ;Inner loop for each source vector
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mov ptr, [arg2+tmp*PS] ; get pointer to next vect
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pxor xp1, xs1 ; p1 ^= s1
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pxor xp2, xs2 ; p2 ^= s2
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pxor xq1, xs1 ; q1 ^= s1
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pxor xq2, xs2 ; q2 ^= s2
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pxor xtmp1, xtmp1 ; xtmp1 = 0 - for compare to 0
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pxor xtmp2, xtmp2 ; xtmp2 = 0
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pcmpgtb xtmp1, xq1 ; xtmp1 = mask 0xff or 0x00 if bit7 set
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pcmpgtb xtmp2, xq2 ; xtmp2 = mask 0xff or 0x00 if bit7 set
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pand xtmp1, xpoly ; xtmp1 = poly or 0x00
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pand xtmp2, xpoly ; xtmp2 = poly or 0x00
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XLDR xs1, [ptr+pos] ; Get next vector (source data1)
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XLDR xs2, [ptr+pos+16] ; Get next vector (source data2)
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paddb xq1, xq1 ; q1 = q1<<1
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paddb xq2, xq2 ; q2 = q2<<1
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pxor xq1, xtmp1 ; q1 = q1<<1 ^ poly_masked
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pxor xq2, xtmp2 ; q2 = q2<<1 ^ poly_masked
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jg next_vect ; Loop for each vect except 0
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pxor xp1, xs1 ;p1 ^= s1[0] - last source is already loaded
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pxor xq1, xs1 ;q1 ^= 1 * s1[0]
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pxor xp2, xs2 ;p2 ^= s2[0]
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pxor xq2, xs2 ;q2 ^= 1 * s2[0]
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mov tmp, [arg2+(2*PS)+vec*PS] ;Get address of Q parity vector
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XLDR xtmp1, [tmp+pos] ;re-init xq1 with Q1 src
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XLDR xtmp2, [tmp+pos+16] ;re-init xq2 with Q2 src + 16B ahead
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pxor xq1, xtmp1 ;xq1 = q1 calculated ^ q1 saved
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pxor xq2, xtmp2
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por xp1, xq1 ;Confirm that all P&Q parity are 0
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por xp1, xp2
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por xp1, xq2
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ptest xp1, xp1
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jnz return_fail
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add pos, 32
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cmp pos, len
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jle loop32
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;; ------------------------------
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;; Do last 16 Bytes remaining
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add len, 32
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cmp pos, len
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je return_pass
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loop16:
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mov ptr, [arg2+PS+vec*PS] ;Get address of P parity vector
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mov tmp, [arg2+(2*PS)+vec*PS] ;Get address of Q parity vector
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XLDR xp1, [ptr+pos] ;Initialize xp1 with P1 src
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pxor xq1, xq1 ;q = 0
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mov ptr, [arg2+vec*PS] ;Fetch last source pointer
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mov tmp, vec ;Set tmp to point back to last vector
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XLDR xs1, [ptr+pos] ;Preload last vector (source)
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next_vect16:
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sub tmp, 1 ;Inner loop for each source vector
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mov ptr, [arg2+tmp*PS] ; get pointer to next vect
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pxor xq1, xs1 ; q ^= s
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pxor xtmp1, xtmp1 ; xtmp = 0
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pcmpgtb xtmp1, xq1 ; xtmp = mask 0xff or 0x00 if bit7 set
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pand xtmp1, xpoly ; xtmp = poly or 0x00
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pxor xp1, xs1 ; p ^= s
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paddb xq1, xq1 ; q = q<<1
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pxor xq1, xtmp1 ; q = q<<1 ^ poly_masked
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XLDR xs1, [ptr+pos] ; Get next vector (source data)
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jg next_vect16 ; Loop for each vect except 0
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pxor xp1, xs1 ;p ^= s[0] - last source is already loaded
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pxor xq1, xs1 ;q ^= 1 * s[0]
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mov tmp, [arg2+(2*PS)+vec*PS] ;Get address of Q parity vector
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XLDR xtmp1, [tmp+pos] ;re-init tmp with Q1 src
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pxor xq1, xtmp1 ;xq1 = q1 calculated ^ q1 saved
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por xp1, xq1 ;Confirm that all P&Q parity are = 0
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ptest xp1, xp1
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jnz return_fail
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add pos, 16
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cmp pos, len
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jl loop16
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return_pass:
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mov return, 0
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FUNC_RESTORE
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ret
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return_fail:
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mov return, 1
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FUNC_RESTORE
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ret
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endproc_frame
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section .data
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align 16
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poly:
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dq 0x1d1d1d1d1d1d1d1d, 0x1d1d1d1d1d1d1d1d
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;;; func core, ver, snum
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slversion pq_check_sse, 00, 06, 0033
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