isa-l/erasure_code/ppc64le
Pablo de Lara e0fd782974 erasure_code: use internal gf_vect_mul_base for ppc64le encoding
gf_vect_mul_base is expected to work for all buffer sizes.
However, this function is checking for size alignment to 32 bytes,
to follow the other gf_vect_mul implementations.
Therefore, another implementation for this function is included
inside ppc64le folder to be used by the encoding functions.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2024-01-15 15:48:14 +00:00
..
ec_base_vsx.c erasure_code: check for size alignment on powerpc gf_vect_mul_vsx implementation 2024-01-15 15:48:14 +00:00
ec_base_vsx.h enable VSX SIMD in ISA-L for ppc64le 2020-02-20 09:40:43 -07:00
gf_2vect_dot_prod_vsx.c enable VSX SIMD in ISA-L for ppc64le 2020-02-20 09:40:43 -07:00
gf_2vect_mad_vsx.c enable VSX SIMD in ISA-L for ppc64le 2020-02-20 09:40:43 -07:00
gf_3vect_dot_prod_vsx.c enable VSX SIMD in ISA-L for ppc64le 2020-02-20 09:40:43 -07:00
gf_3vect_mad_vsx.c enable VSX SIMD in ISA-L for ppc64le 2020-02-20 09:40:43 -07:00
gf_4vect_dot_prod_vsx.c enable VSX SIMD in ISA-L for ppc64le 2020-02-20 09:40:43 -07:00
gf_4vect_mad_vsx.c enable VSX SIMD in ISA-L for ppc64le 2020-02-20 09:40:43 -07:00
gf_5vect_dot_prod_vsx.c enable VSX SIMD in ISA-L for ppc64le 2020-02-20 09:40:43 -07:00
gf_5vect_mad_vsx.c enable VSX SIMD in ISA-L for ppc64le 2020-02-20 09:40:43 -07:00
gf_6vect_dot_prod_vsx.c enable VSX SIMD in ISA-L for ppc64le 2020-02-20 09:40:43 -07:00
gf_6vect_mad_vsx.c enable VSX SIMD in ISA-L for ppc64le 2020-02-20 09:40:43 -07:00
gf_vect_dot_prod_vsx.c enable VSX SIMD in ISA-L for ppc64le 2020-02-20 09:40:43 -07:00
gf_vect_mad_vsx.c enable VSX SIMD in ISA-L for ppc64le 2020-02-20 09:40:43 -07:00
gf_vect_mul_vsx.c erasure_code: use internal gf_vect_mul_base for ppc64le encoding 2024-01-15 15:48:14 +00:00
Makefile.am enable VSX SIMD in ISA-L for ppc64le 2020-02-20 09:40:43 -07:00