mirror of
https://github.com/intel/isa-l.git
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1187583a97
- It should be fine to enable pmull always on Apple Silicon - macOS 12+ is required for PMULL instruction. - Changed the conditional macro to __APPLE__ - Rewritten dispatcher using sysctlbyname - Use __USER_LABEL_PREFIX__ - Use __TEXT,__const as readonly section - use ASM_DEF_RODATA macro - fix func decl Change-Id: I800593f21085d8187b480c8bb3ab2bd70c4a6974 Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>
127 lines
3.4 KiB
ArmAsm
127 lines
3.4 KiB
ArmAsm
/**************************************************************
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Copyright (c) 2021 Linaro Ltd.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Huawei Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**********************************************************************/
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.text
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.align 6
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.arch armv8-a+sve
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#include "../include/aarch64_label.h"
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.global cdecl(gf_vect_mad_sve)
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#ifndef __APPLE__
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.type gf_vect_mad_sve, %function
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#endif
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/* gf_vect_mad_sve(int len, int vec, int vec_i, unsigned char *gftbls,
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unsigned char *src, unsigned char *dest);
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*/
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/* arguments */
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x_len .req x0
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x_vec .req x1
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x_vec_i .req x2
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x_tbl .req x3
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x_src .req x4
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x_dest .req x5
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/* returns */
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w_ret .req w0
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/* local variables */
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x_pos .req x6
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/* vectors */
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z_mask0f .req z0
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z_src .req z1
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z_src_lo .req z2
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z_src_hi .req z_src
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z_dest .req z3
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z_tmp1_lo .req z4
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z_tmp1_hi .req z5
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z_gft1_lo .req z6
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z_gft1_hi .req z7
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q_gft1_lo .req q6
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q_gft1_hi .req q7
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cdecl(gf_vect_mad_sve):
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/* less than 16 bytes, return_fail */
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cmp x_len, #16
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blt .return_fail
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mov z_mask0f.b, #0x0f /* z_mask0f = 0x0F0F...0F */
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add x_tbl, x_tbl, x_vec_i, LSL #5 /* x_tbl += x_vec_i * 2^5 */
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/* Load with NEON instruction ldp */
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ldp q_gft1_lo, q_gft1_hi, [x_tbl]
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mov x_pos, #0
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/* vector length agnostic */
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.Lloopsve_vl:
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whilelo p0.b, x_pos, x_len
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b.none .return_pass
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/* prefetch dest data */
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prfb pldl2strm, p0, [x_dest, x_pos]
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/* load src data, governed by p0 */
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ld1b z_src.b, p0/z, [x_src, x_pos]
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/* split 4-bit lo; 4-bit hi */
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and z_src_lo.d, z_src.d, z_mask0f.d
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lsr z_src_hi.b, z_src.b, #4
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/* load dest data, governed by p0 */
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ld1b z_dest.b, p0/z, [x_dest, x_pos]
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/* table indexing, ie. gf(2^8) multiplication */
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tbl z_tmp1_lo.b, {z_gft1_lo.b}, z_src_lo.b
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tbl z_tmp1_hi.b, {z_gft1_hi.b}, z_src_hi.b
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/* exclusive or, ie. gf(2^8) add */
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eor z_dest.d, z_tmp1_lo.d, z_dest.d
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eor z_dest.d, z_tmp1_hi.d, z_dest.d
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/* store dest data, governed by p0 */
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st1b z_dest.b, p0, [x_dest, x_pos]
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/* increment one vector length */
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incb x_pos
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b .Lloopsve_vl
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.return_pass:
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mov w_ret, #0
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ret
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.return_fail:
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mov w_ret, #1
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ret
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