mirror of
https://github.com/intel/isa-l.git
synced 2024-12-14 02:05:11 +01:00
1187583a97
- It should be fine to enable pmull always on Apple Silicon - macOS 12+ is required for PMULL instruction. - Changed the conditional macro to __APPLE__ - Rewritten dispatcher using sysctlbyname - Use __USER_LABEL_PREFIX__ - Use __TEXT,__const as readonly section - use ASM_DEF_RODATA macro - fix func decl Change-Id: I800593f21085d8187b480c8bb3ab2bd70c4a6974 Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>
102 lines
3.0 KiB
ArmAsm
102 lines
3.0 KiB
ArmAsm
########################################################################
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# Copyright(c) 2020 Arm Corporation All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in
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# the documentation and/or other materials provided with the
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# distribution.
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# * Neither the name of Arm Corporation nor the names of its
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# contributors may be used to endorse or promote products derived
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# from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#########################################################################
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.text
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.align 6
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.arch armv8-a+crc+crypto
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#include "crc32_aarch64_common.h"
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.macro crc32_u64 dst,src,data
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crc32cx \dst,\src,\data
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.endm
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.macro crc32_u32 dst,src,data
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crc32cw \dst,\src,\data
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.endm
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.macro crc32_u16 dst,src,data
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crc32ch \dst,\src,\data
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.endm
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.macro crc32_u8 dst,src,data
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crc32cb \dst,\src,\data
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.endm
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.macro declare_var_vector_reg name:req,reg:req
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q\name .req q\reg
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v\name .req v\reg
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s\name .req s\reg
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d\name .req d\reg
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.endm
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BUF .req x0
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LEN .req x1
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wCRC .req w2
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crc0 .req w2
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crc1 .req w3
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crc2 .req w4
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xcrc0 .req x2
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xcrc1 .req x3
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const_adr .req x3
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ptr_crc0 .req x0
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ptr_crc1 .req x6
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ptr_crc2 .req x7
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crc0_data0 .req x9
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crc0_data1 .req x10
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crc1_data0 .req x11
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crc1_data1 .req x12
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crc2_data0 .req x13
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crc2_data1 .req x14
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wdata .req w3
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data0 .req x3
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data1 .req x4
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data2 .req x5
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data3 .req x6
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declare_var_vector_reg tmp0,0
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declare_var_vector_reg tmp1,1
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declare_var_vector_reg const0,2
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declare_var_vector_reg const1,3
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/**
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unsigned int crc32_iscsi(
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unsigned char *BUF,
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int LEN,
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unsigned int wCRC
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);
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*/
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.global cdecl(crc32_iscsi_3crc_fold)
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#ifndef __APPLE__
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.type crc32_iscsi_3crc_fold, %function
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#endif
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cdecl(crc32_iscsi_3crc_fold):
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crc32_3crc_fold crc32c
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#ifndef __APPLE__
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.size crc32_iscsi_3crc_fold, .-crc32_iscsi_3crc_fold
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#endif
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