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bc34d87427
Signed-off-by: Marcel Cornu <marcel.d.cornu@intel.com>
73 lines
2.6 KiB
PHP
73 lines
2.6 KiB
PHP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2023 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Multiply 1 source register to up to 6 different GF table registers
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; and XOR the results to partial registers
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;
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%macro GF_MUL_XOR 5-20
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%define %%ENCODING %1
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%define %%SRC %2
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%define %%GFTABLE1 %3
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%define %%TMP1 %4
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%define %%PARTIAL1 %5
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%define %%GFTABLE2 %6
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%define %%TMP2 %7
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%define %%PARTIAL2 %8
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%define %%GFTABLE3 %9
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%define %%TMP3 %10
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%define %%PARTIAL3 %11
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%define %%GFTABLE4 %12
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%define %%TMP4 %13
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%define %%PARTIAL4 %14
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%define %%GFTABLE5 %15
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%define %%TMP5 %16
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%define %%PARTIAL5 %17
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%define %%GFTABLE6 %18
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%define %%TMP6 %19
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%define %%PARTIAL6 %20
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%define %%N_BLOCKS ((%0 - 2) / 3)
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%assign %%I 1
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%rep %%N_BLOCKS
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vgf2p8affineqb %%TMP %+ %%I, %%SRC, %%GFTABLE %+ %%I, 0x00
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%assign %%I (%%I + 1)
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%endrep
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%assign %%I 1
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%rep %%N_BLOCKS
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%ifidn %%ENCODING, VEX
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vpxor %%PARTIAL %+ %%I, %%TMP %+ %%I
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%else
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vpxorq %%PARTIAL %+ %%I, %%TMP %+ %%I
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%endif
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%assign %%I (%%I + 1)
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%endrep
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%endmacro
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