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a46da529d9
Change-Id: I49166ee06b3ad24babb90aeb0b834d8aacfc2d03 Signed-off-by: Zhiyuan Zhu <zhiyuan.zhu@arm.com>
311 lines
7.4 KiB
C
311 lines
7.4 KiB
C
########################################################################
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# Copyright(c) 2019 Arm Corporation All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in
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# the documentation and/or other materials provided with the
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# distribution.
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# * Neither the name of Arm Corporation nor the names of its
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# contributors may be used to endorse or promote products derived
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# from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#########################################################################
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.macro crc64_norm_func name:req
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.arch armv8-a+crc+crypto
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.text
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.align 3
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.global \name
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.type \name, %function
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/* uint64_t crc64_norm_func(uint64_t seed, const uint8_t * buf, uint64_t len) */
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// parameter
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x_seed .req x0
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x_buf .req x1
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x_len .req x2
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// return
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x_crc_ret .req x0
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// constant
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.equ FOLD_SIZE, 1024
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// global variables
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x_buf_end .req x3 // buffer address with truncated
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x_counter .req x4
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x_buf_iter .req x5
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x_crc64_tab_addr .req x9
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w_tmp .req w6
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x_tmp .req x6
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w_tmp1 .req w7
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x_tmp1 .req x7
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\name\():
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mvn x_seed, x_seed
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mov x_counter, 0
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cmp x_len, (FOLD_SIZE-1)
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bhi .crc64_clmul_pre
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.crc64_tab_pre:
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cmp x_len, x_counter
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bls .done
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adrp x_tmp, lanchor_crc64_tab
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add x_buf_iter, x_buf, x_counter
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add x_buf, x_buf, x_len
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add x_crc64_tab_addr, x_tmp, :lo12:lanchor_crc64_tab
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.align 3
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.loop_crc64_tab:
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ldrb w_tmp, [x_buf_iter], 1
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cmp x_buf, x_buf_iter
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eor x_tmp, x_tmp, x_seed, lsr 56
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ldr x_tmp, [x_crc64_tab_addr, x_tmp, lsl 3]
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eor x_seed, x_tmp, x_seed, lsl 8
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bne .loop_crc64_tab
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.done:
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mvn x_crc_ret, x_seed
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ret
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d_tmp .req d3
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q_tmp .req q3
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v_tmp .req v3
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q_x0 .req q2
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q_x1 .req q16
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q_x2 .req q6
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q_x3 .req q4
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v_x0 .req v2
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v_x1 .req v16
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v_x2 .req v6
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v_x3 .req v4
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d_p4_low .req d3
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d_p4_high .req d5
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v_p4_low .req v3
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v_p4_high .req v5
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q_shuffle .req q1
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v_shuffle .req v1
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.align 2
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.crc64_clmul_pre:
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adrp x_tmp, .shuffle_data
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ldr q_shuffle, [x_tmp, #:lo12:.shuffle_data]
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and x_counter, x_len, -64
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sub x_tmp1, x_counter, #64
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cmp x_tmp1, 63 // align and the truncated buffer size
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movi v_x0.4s, 0
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ins v_x0.d[1], x_seed
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add x_buf_iter, x_buf, 64
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ldr q_tmp, [x_buf]
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ldr q_x1, [x_buf, 16]
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ldr q_x2, [x_buf, 32]
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ldr q_x3, [x_buf, 48]
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tbl v_tmp.16b, {v_tmp.16b}, v_shuffle.16b
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tbl v_x1.16b, {v_x1.16b}, v_shuffle.16b
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tbl v_x2.16b, {v_x2.16b}, v_shuffle.16b
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tbl v_x3.16b, {v_x3.16b}, v_shuffle.16b
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eor v_x0.16b, v_x0.16b, v_tmp.16b
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bls .clmul_loop_end
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mov x_tmp, p4_high_b0
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movk x_tmp, p4_high_b1, lsl 16
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movk x_tmp, p4_high_b2, lsl 32
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movk x_tmp, p4_high_b3, lsl 48
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fmov d_p4_high, x_tmp
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mov x_tmp, p4_low_b0
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movk x_tmp, p4_low_b1, lsl 16
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movk x_tmp, p4_low_b2, lsl 32
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movk x_tmp, p4_low_b3, lsl 48
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fmov d_p4_low, x_tmp
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add x_buf_end, x_buf_iter, x_tmp1
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// 1024bit --> 512bit loop
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// merge x0, x1, x2, x3, y0, y1, y2, y3 => x0, x1, x2, x3 (uint64x2_t)
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d_x0_high .req d24
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d_x1_high .req d22
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d_x2_high .req d20
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d_x3_high .req d18
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v_x0_high .req v24
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v_x1_high .req v22
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v_x2_high .req v20
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v_x3_high .req v18
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q_y0 .req q17
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q_y1 .req q19
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q_y2 .req q7
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q_y3 .req q0
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v_y0 .req v17
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v_y1 .req v19
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v_y2 .req v7
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v_y3 .req v0
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.align 3
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.clmul_loop:
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dup d_x0_high, v_x0.d[1]
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dup d_x1_high, v_x1.d[1]
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dup d_x2_high, v_x2.d[1]
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dup d_x3_high, v_x3.d[1]
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add x_buf_iter, x_buf_iter, 64
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cmp x_buf_iter, x_buf_end
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ldr q_y0, [x_buf_iter, -64]
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ldr q_y1, [x_buf_iter, -48]
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ldr q_y2, [x_buf_iter, -32]
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ldr q_y3, [x_buf_iter, -16]
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pmull v_x0.1q, v_x0.1d, v_p4_low.1d
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pmull v_x1.1q, v_x1.1d, v_p4_low.1d
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pmull v_x2.1q, v_x2.1d, v_p4_low.1d
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pmull v_x3.1q, v_x3.1d, v_p4_low.1d
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pmull v_x0_high.1q, v_x0_high.1d, v_p4_high.1d
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pmull v_x1_high.1q, v_x1_high.1d, v_p4_high.1d
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pmull v_x2_high.1q, v_x2_high.1d, v_p4_high.1d
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pmull v_x3_high.1q, v_x3_high.1d, v_p4_high.1d
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tbl v_y0.16b, {v_y0.16b}, v_shuffle.16b
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tbl v_y1.16b, {v_y1.16b}, v_shuffle.16b
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tbl v_y2.16b, {v_y2.16b}, v_shuffle.16b
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tbl v_y3.16b, {v_y3.16b}, v_shuffle.16b
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eor v_x0_high.16b, v_x0_high.16b, v_x0.16b
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eor v_x1_high.16b, v_x1_high.16b, v_x1.16b
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eor v_x2_high.16b, v_x2_high.16b, v_x2.16b
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eor v_x3_high.16b, v_x3_high.16b, v_x3.16b
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eor v_x0.16b, v_x0_high.16b, v_y0.16b
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eor v_x1.16b, v_x1_high.16b, v_y1.16b
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eor v_x2.16b, v_x2_high.16b, v_y2.16b
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eor v_x3.16b, v_x3_high.16b, v_y3.16b
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bne .clmul_loop
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// folding 512bit --> 128bit
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// merge x0, x1, x2, x3 => x0 (uint64x2_t)
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d_tmp1 .req d18
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v_tmp1 .req v18
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d_p1_high .req d5
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v_p1_high .req v5
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d_p1_low .req d3
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v_p1_low .req v3
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.clmul_loop_end:
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mov x_tmp, p1_high_b0
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movk x_tmp, p1_high_b1, lsl 16
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movk x_tmp, p1_high_b2, lsl 32
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movk x_tmp, p1_high_b3, lsl 48
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fmov d_p1_high, x_tmp
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mov x_tmp, p1_low_b0
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movk x_tmp, p1_low_b1, lsl 16
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movk x_tmp, p1_low_b2, lsl 32
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movk x_tmp, p1_low_b3, lsl 48
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fmov d_p1_low, x_tmp
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dup d_tmp1, v_x0.d[1]
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pmull v_x0.1q, v_x0.1d, v_p1_low.1d
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pmull v_tmp1.1q, v_tmp1.1d, v_p1_high.1d
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eor v_x0.16b, v_tmp1.16b, v_x0.16b
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eor v_x1.16b, v_x0.16b, v_x1.16b
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dup d_tmp1, v_x1.d[1]
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pmull v_x1.1q, v_x1.1d, v_p1_low.1d
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pmull v_tmp1.1q, v_tmp1.1d, v_p1_high.1d
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eor v_tmp1.16b, v_tmp1.16b, v_x1.16b
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eor v_x2.16b, v_tmp1.16b, v_x2.16b
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dup d_tmp1, v_x2.d[1]
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pmull v_x2.1q, v_x2.1d, v_p1_low.1d
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pmull v_tmp1.1q, v_tmp1.1d, v_p1_high.1d
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eor v_x2.16b, v_tmp1.16b, v_x2.16b
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eor v_x3.16b, v_x2.16b, v_x3.16b
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// fold 64b
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d_p0_low .req d3
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v_p0_low .req v3
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d_x3_high1 .req d2
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v_x3_high1 .req v2
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mov x_tmp, p0_low_b0
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movk x_tmp, p0_low_b1, lsl 16
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movk x_tmp, p0_low_b2, lsl 32
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movk x_tmp, p0_low_b3, lsl 48
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fmov d_p0_low, x_tmp
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dup d_x3_high1, v_x3.d[1]
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movi v0.4s, 0
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ext v0.16b, v0.16b, v_x3.16b, #8
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pmull v_x3_high1.1q, v_x3_high1.1d, v_p0_low.1d
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eor v0.16b, v0.16b, v_x3_high1.16b
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// barrett reduction
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mov x_tmp, br_low_b0
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movk x_tmp, br_low_b1, lsl 16
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movk x_tmp, br_low_b2, lsl 32
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movk x_tmp, br_low_b3, lsl 48
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movi v1.4s, 0x0
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mov x_tmp1, -1
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ins v1.d[1], x_tmp1
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and v2.16b, v1.16b, v0.16b
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fmov d1, x_tmp
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dup d4, v0.d[1]
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pmull v4.1q, v4.1d, v1.1d
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mov x_tmp, br_high_b0
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movk x_tmp, br_high_b1, lsl 16
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movk x_tmp, br_high_b2, lsl 32
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movk x_tmp, br_high_b3, lsl 48
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fmov d1, x_tmp
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eor v2.16b, v2.16b, v4.16b
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dup d2, v2.d[1]
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pmull v2.1q, v2.1d, v1.1d
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eor v0.16b, v0.16b, v2.16b
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umov x_seed, v0.d[0]
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b .crc64_tab_pre
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.size \name, .-\name
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.section .rodata.cst16,"aM",@progbits,16
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.align 4
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.shuffle_data:
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.byte 15, 14, 13, 12, 11, 10, 9, 8
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.byte 7, 6, 5, 4, 3, 2, 1, 0
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.endm
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