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cd888f01a4
To support Intel CET, all indirect branch targets must start with ENDBR32/ENDBR64. Here is a patch to define endbranch and add it to function entries in x86 assembly codes which are indirect branch targets as discovered by running testsuite on Intel CET machine and visual inspection. Verified with $ CC="gcc -Wl,-z,cet-report=error -fcf-protection" CXX="g++ -Wl,-z,cet-report=error -fcf-protection" .../configure x86_64-linux $ make -j8 $ make -j8 check with both nasm and yasm on both CET and non-CET machines. Change-Id: I9822578e7294fb5043a64ab7de5c41de81a7d337 Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
194 lines
5.0 KiB
NASM
194 lines
5.0 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; gf_vect_mad_avx512(len, vec, vec_i, mul_array, src, dest);
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;;;
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%include "reg_sizes.asm"
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%ifdef HAVE_AS_KNOWS_AVX512
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%ifidn __OUTPUT_FORMAT__, elf64
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%define arg0 rdi
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%define arg1 rsi
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%define arg2 rdx
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%define arg3 rcx
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%define arg4 r8
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%define arg5 r9
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%define tmp r11
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%define return rax
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%define func(x) x: endbranch
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%define FUNC_SAVE
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%define FUNC_RESTORE
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%endif
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%ifidn __OUTPUT_FORMAT__, win64
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%define arg0 rcx
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%define arg1 rdx
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%define arg2 r8
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%define arg3 r9
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%define arg4 r12 ; must be saved and loaded
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%define arg5 r15
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%define tmp r11
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%define return rax
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%define PS 8
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%define stack_size 16*3 + 3*8
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%define arg(x) [rsp + stack_size + PS + PS*x]
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%define func(x) proc_frame x
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%macro FUNC_SAVE 0
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sub rsp, stack_size
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vmovdqa [rsp+16*0],xmm6
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vmovdqa [rsp+16*1],xmm7
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vmovdqa [rsp+16*2],xmm8
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save_reg r12, 3*16 + 0*8
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save_reg r15, 3*16 + 1*8
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end_prolog
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mov arg4, arg(4)
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mov arg5, arg(5)
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%endmacro
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%macro FUNC_RESTORE 0
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vmovdqa xmm6, [rsp+16*0]
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vmovdqa xmm7, [rsp+16*1]
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vmovdqa xmm8, [rsp+16*2]
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mov r12, [rsp + 3*16 + 0*8]
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mov r15, [rsp + 3*16 + 1*8]
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add rsp, stack_size
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%endmacro
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%endif
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;;; gf_vect_mad_avx512(len, vec, vec_i, mul_array, src, dest)
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%define len arg0
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%define vec arg1
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%define vec_i arg2
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%define mul_array arg3
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%define src arg4
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%define dest arg5
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%define pos return
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%ifndef EC_ALIGNED_ADDR
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;;; Use Un-aligned load/store
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%define XLDR vmovdqu8
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%define XSTR vmovdqu8
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%else
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;;; Use Non-temporal load/stor
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%ifdef NO_NT_LDST
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%define XLDR vmovdqa
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%define XSTR vmovdqa
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%else
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%define XLDR vmovntdqa
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%define XSTR vmovntdq
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%endif
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%endif
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default rel
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[bits 64]
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section .text
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%define x0 zmm0
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%define xtmpa zmm1
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%define xtmph zmm2
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%define xtmpl zmm3
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%define xd zmm4
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%define xtmpd zmm5
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%define xgft_hi zmm6
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%define xgft_lo zmm7
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%define xgft_loy ymm7
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%define xmask0f zmm8
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align 16
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mk_global gf_vect_mad_avx512, function
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func(gf_vect_mad_avx512)
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FUNC_SAVE
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sub len, 64
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jl .return_fail
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xor pos, pos
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mov tmp, 0x0f
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vpbroadcastb xmask0f, tmp ;Construct mask 0x0f0f0f...
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sal vec_i, 5 ;Multiply by 32
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vmovdqu8 xgft_loy, [vec_i+mul_array] ;Load array Cx{00}..{0f}, Cx{00}..{f0}
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vshufi64x2 xgft_hi, xgft_lo, xgft_lo, 0x55
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vshufi64x2 xgft_lo, xgft_lo, xgft_lo, 0x00
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mov tmp, -1
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kmovq k1, tmp
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.loop64:
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XLDR xd, [dest+pos] ;Get next dest vector
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XLDR x0, [src+pos] ;Get next source vector
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vpandq xtmpa, x0, xmask0f ;Mask low src nibble in bits 4-0
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vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
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vpandq x0, x0, xmask0f ;Mask high src nibble in bits 4-0
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vpshufb xtmph {k1}{z}, xgft_hi, x0 ;Lookup mul table of high nibble
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vpshufb xtmpl {k1}{z}, xgft_lo, xtmpa ;Lookup mul table of low nibble
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vpxorq xtmph, xtmph, xtmpl ;GF add high and low partials
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vpxorq xd, xd, xtmph ;xd += partial
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XSTR [dest+pos], xd
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add pos, 64 ;Loop on 64 bytes at a time
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cmp pos, len
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jle .loop64
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lea tmp, [len + 64]
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cmp pos, tmp
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je .return_pass
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;; Tail len
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mov pos, (1 << 63)
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lea tmp, [len + 64 - 1]
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and tmp, 63
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sarx pos, pos, tmp
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kmovq k1, pos
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mov pos, len ;Overlapped offset length-64
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jmp .loop64 ;Do one more overlap pass
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.return_pass:
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mov return, 0
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FUNC_RESTORE
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ret
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.return_fail:
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mov return, 1
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FUNC_RESTORE
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ret
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endproc_frame
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%else
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%ifidn __OUTPUT_FORMAT__, win64
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global no_gf_vect_mad_avx512
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no_gf_vect_mad_avx512:
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%endif
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%endif ; ifdef HAVE_AS_KNOWS_AVX512
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