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fc1467deb2
Change-Id: I114bfcfa8750c7ba3a50ad2be9dd9e87cb7a1042 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
268 lines
7.5 KiB
NASM
268 lines
7.5 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; gf_4vect_mad_avx512(len, vec, vec_i, mul_array, src, dest);
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;;;
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%include "reg_sizes.asm"
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%ifdef HAVE_AS_KNOWS_AVX512
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%ifidn __OUTPUT_FORMAT__, elf64
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%define arg0 rdi
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%define arg1 rsi
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%define arg2 rdx
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%define arg3 rcx
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%define arg4 r8
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%define arg5 r9
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%define tmp r11
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%define return rax
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%define func(x) x:
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%define FUNC_SAVE
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%define FUNC_RESTORE
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%endif
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%ifidn __OUTPUT_FORMAT__, win64
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%define arg0 rcx
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%define arg1 rdx
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%define arg2 r8
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%define arg3 r9
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%define arg4 r12
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%define arg5 r15
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%define tmp r11
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%define return rax
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%define stack_size 16*10 + 3*8
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%define arg(x) [rsp + stack_size + PS + PS*x]
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%define func(x) proc_frame x
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%macro FUNC_SAVE 0
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sub rsp, stack_size
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movdqa [rsp+16*0],xmm6
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movdqa [rsp+16*1],xmm7
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movdqa [rsp+16*2],xmm8
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movdqa [rsp+16*3],xmm9
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movdqa [rsp+16*4],xmm10
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movdqa [rsp+16*5],xmm11
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movdqa [rsp+16*6],xmm12
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movdqa [rsp+16*7],xmm13
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movdqa [rsp+16*8],xmm14
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movdqa [rsp+16*9],xmm15
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save_reg r12, 10*16 + 0*8
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save_reg r15, 10*16 + 1*8
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end_prolog
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mov arg4, arg(4)
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mov arg5, arg(5)
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%endmacro
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%macro FUNC_RESTORE 0
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movdqa xmm6, [rsp+16*0]
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movdqa xmm7, [rsp+16*1]
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movdqa xmm8, [rsp+16*2]
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movdqa xmm9, [rsp+16*3]
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movdqa xmm10, [rsp+16*4]
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movdqa xmm11, [rsp+16*5]
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movdqa xmm12, [rsp+16*6]
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movdqa xmm13, [rsp+16*7]
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movdqa xmm14, [rsp+16*8]
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movdqa xmm15, [rsp+16*9]
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mov r12, [rsp + 10*16 + 0*8]
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mov r15, [rsp + 10*16 + 1*8]
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add rsp, stack_size
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%endmacro
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%endif
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%define PS 8
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%define len arg0
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%define vec arg1
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%define vec_i arg2
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%define mul_array arg3
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%define src arg4
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%define dest1 arg5
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%define pos return
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%define dest2 mul_array
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%define dest3 vec
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%define dest4 vec_i
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%ifndef EC_ALIGNED_ADDR
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;;; Use Un-aligned load/store
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%define XLDR vmovdqu8
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%define XSTR vmovdqu8
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%else
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;;; Use Non-temporal load/stor
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%ifdef NO_NT_LDST
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%define XLDR vmovdqa
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%define XSTR vmovdqa
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%else
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%define XLDR vmovntdqa
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%define XSTR vmovntdq
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%endif
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%endif
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default rel
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[bits 64]
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section .text
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%define x0 zmm0
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%define xtmpa zmm1
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%define xtmpl1 zmm2
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%define xtmph1 zmm3
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%define xtmph2 zmm4
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%define xtmph3 zmm5
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%define xtmph4 zmm6
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%define xgft1_hi zmm7
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%define xgft1_lo zmm8
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%define xgft1_loy ymm8
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%define xgft2_hi zmm9
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%define xgft2_lo zmm10
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%define xgft2_loy ymm10
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%define xgft3_hi zmm11
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%define xgft3_lo zmm12
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%define xgft3_loy ymm12
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%define xgft4_hi zmm13
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%define xgft4_lo zmm14
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%define xgft4_loy ymm14
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%define xd1 zmm15
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%define xd2 zmm16
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%define xd3 zmm17
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%define xd4 zmm18
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%define xmask0f zmm19
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%define xtmpl2 zmm20
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%define xtmpl3 zmm21
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%define xtmpl4 zmm22
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%define xtmpl5 zmm23
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align 16
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global gf_4vect_mad_avx512:function
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func(gf_4vect_mad_avx512)
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FUNC_SAVE
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sub len, 64
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jl .return_fail
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xor pos, pos
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mov tmp, 0x0f
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vpbroadcastb xmask0f, tmp ;Construct mask 0x0f0f0f...
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sal vec_i, 5 ;Multiply by 32
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sal vec, 5 ;Multiply by 32
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lea tmp, [mul_array + vec_i]
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vmovdqu xgft1_loy, [tmp] ;Load array Ax{00}..{0f}, Ax{00}..{f0}
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vmovdqu xgft2_loy, [tmp+vec] ;Load array Bx{00}..{0f}, Bx{00}..{f0}
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vmovdqu xgft3_loy, [tmp+2*vec] ;Load array Cx{00}..{0f}, Cx{00}..{f0}
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add tmp, vec
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vmovdqu xgft4_loy, [tmp+2*vec] ;Load array Dx{00}..{0f}, Dx{00}..{f0}
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vshufi64x2 xgft1_hi, xgft1_lo, xgft1_lo, 0x55
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vshufi64x2 xgft1_lo, xgft1_lo, xgft1_lo, 0x00
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vshufi64x2 xgft2_hi, xgft2_lo, xgft2_lo, 0x55
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vshufi64x2 xgft2_lo, xgft2_lo, xgft2_lo, 0x00
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vshufi64x2 xgft3_hi, xgft3_lo, xgft3_lo, 0x55
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vshufi64x2 xgft3_lo, xgft3_lo, xgft3_lo, 0x00
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vshufi64x2 xgft4_hi, xgft4_lo, xgft4_lo, 0x55
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vshufi64x2 xgft4_lo, xgft4_lo, xgft4_lo, 0x00
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mov dest2, [dest1+PS] ; reuse mul_array
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mov dest3, [dest1+2*PS] ; reuse vec
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mov dest4, [dest1+3*PS] ; reuse vec_i
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mov dest1, [dest1]
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mov tmp, -1
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kmovq k1, tmp
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.loop64:
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XLDR x0, [src+pos] ;Get next source vector
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XLDR xd1, [dest1+pos] ;Get next dest vector
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XLDR xd2, [dest2+pos] ;Get next dest vector
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XLDR xd3, [dest3+pos] ;Get next dest vector
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XLDR xd4, [dest4+pos] ;reuse xtmpl1. Get next dest vector
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vpandq xtmpa, x0, xmask0f ;Mask low src nibble in bits 4-0
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vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
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vpandq x0, x0, xmask0f ;Mask high src nibble in bits 4-0
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; dest1
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vpshufb xtmph1 {k1}{z}, xgft1_hi, x0 ;Lookup mul table of high nibble
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vpshufb xtmpl1 {k1}{z}, xgft1_lo, xtmpa ;Lookup mul table of low nibble
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vpxorq xtmph1, xtmph1, xtmpl1 ;GF add high and low partials
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vpxorq xd1, xd1, xtmph1 ;xd1 += partial
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; dest2
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vpshufb xtmph2 {k1}{z}, xgft2_hi, x0 ;Lookup mul table of high nibble
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vpshufb xtmpl2 {k1}{z}, xgft2_lo, xtmpa ;Lookup mul table of low nibble
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vpxorq xtmph2, xtmph2, xtmpl2 ;GF add high and low partials
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vpxorq xd2, xd2, xtmph2 ;xd2 += partial
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; dest3
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vpshufb xtmph3 {k1}{z}, xgft3_hi, x0 ;Lookup mul table of high nibble
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vpshufb xtmpl3 {k1}{z}, xgft3_lo, xtmpa ;Lookup mul table of low nibble
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vpxorq xtmph3, xtmph3, xtmpl3 ;GF add high and low partials
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vpxorq xd3, xd3, xtmph3 ;xd2 += partial
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; dest4
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vpshufb xtmph4 {k1}{z}, xgft4_hi, x0 ;Lookup mul table of high nibble
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vpshufb xtmpl4 {k1}{z}, xgft4_lo, xtmpa ;Lookup mul table of low nibble
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vpxorq xtmph4, xtmph4, xtmpl4 ;GF add high and low partials
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vpxorq xd4, xd4, xtmph4 ;xd2 += partial
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XSTR [dest1+pos], xd1
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XSTR [dest2+pos], xd2
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XSTR [dest3+pos], xd3
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XSTR [dest4+pos], xd4
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add pos, 64 ;Loop on 64 bytes at a time
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cmp pos, len
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jle .loop64
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lea tmp, [len + 64]
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cmp pos, tmp
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je .return_pass
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;; Tail len
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mov pos, (1 << 63)
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lea tmp, [len + 64 - 1]
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and tmp, 63
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sarx pos, pos, tmp
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kmovq k1, pos
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mov pos, len ;Overlapped offset length-64
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jmp .loop64 ;Do one more overlap pass
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.return_pass:
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mov return, 0
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FUNC_RESTORE
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ret
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.return_fail:
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mov return, 1
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FUNC_RESTORE
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ret
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endproc_frame
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%else
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%ifidn __OUTPUT_FORMAT__, win64
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global no_gf_4vect_mad_avx512
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no_gf_4vect_mad_avx512:
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%endif
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%endif ; ifdef HAVE_AS_KNOWS_AVX512
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