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https://github.com/intel/isa-l.git
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fc1467deb2
Change-Id: I114bfcfa8750c7ba3a50ad2be9dd9e87cb7a1042 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
338 lines
7.9 KiB
NASM
338 lines
7.9 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; gf_2vect_dot_prod_avx(len, vec, *g_tbls, **buffs, **dests);
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;;;
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%include "reg_sizes.asm"
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%ifidn __OUTPUT_FORMAT__, elf64
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%define arg0 rdi
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%define arg1 rsi
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%define arg2 rdx
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%define arg3 rcx
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%define arg4 r8
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%define arg5 r9
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%define tmp r11
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%define tmp2 r10
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%define tmp3 r9
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%define tmp4 r12 ; must be saved and restored
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%define return rax
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%macro SLDR 2
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%endmacro
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%define SSTR SLDR
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%define PS 8
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%define LOG_PS 3
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%define func(x) x:
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%macro FUNC_SAVE 0
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push r12
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%endmacro
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%macro FUNC_RESTORE 0
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pop r12
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%endmacro
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%endif
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%ifidn __OUTPUT_FORMAT__, win64
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%define arg0 rcx
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%define arg1 rdx
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%define arg2 r8
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%define arg3 r9
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%define arg4 r12 ; must be saved, loaded and restored
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%define tmp r11
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%define tmp2 r10
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%define tmp3 r13 ; must be saved and restored
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%define tmp4 r14 ; must be saved and restored
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%define return rax
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%macro SLDR 2
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%endmacro
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%define SSTR SLDR
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%define PS 8
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%define LOG_PS 3
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%define stack_size 3*16 + 3*8 ; must be an odd multiple of 8
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%define arg(x) [rsp + stack_size + PS + PS*x]
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%define func(x) proc_frame x
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%macro FUNC_SAVE 0
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alloc_stack stack_size
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save_xmm128 xmm6, 0*16
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save_xmm128 xmm7, 1*16
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save_xmm128 xmm8, 2*16
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save_reg r12, 3*16 + 0*8
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save_reg r13, 3*16 + 1*8
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save_reg r14, 3*16 + 2*8
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end_prolog
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mov arg4, arg(4)
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%endmacro
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%macro FUNC_RESTORE 0
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vmovdqa xmm6, [rsp + 0*16]
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vmovdqa xmm7, [rsp + 1*16]
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vmovdqa xmm8, [rsp + 2*16]
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mov r12, [rsp + 3*16 + 0*8]
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mov r13, [rsp + 3*16 + 1*8]
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mov r14, [rsp + 3*16 + 2*8]
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add rsp, stack_size
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%endmacro
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%endif
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%ifidn __OUTPUT_FORMAT__, elf32
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;;;================== High Address;
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;;; arg4
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;;; arg3
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;;; arg2
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;;; arg1
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;;; arg0
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;;; return
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;;;<================= esp of caller
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;;; ebp
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;;;<================= ebp = esp
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;;; var0
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;;; esi
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;;; edi
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;;; ebx
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;;;<================= esp of callee
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;;;
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;;;================== Low Address;
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%define PS 4
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%define LOG_PS 2
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%define func(x) x:
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%define arg(x) [ebp + PS*2 + PS*x]
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%define var(x) [ebp - PS - PS*x]
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%define trans ecx
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%define trans2 esi
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%define arg0 trans ;trans and trans2 are for the variables in stack
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%define arg0_m arg(0)
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%define arg1 ebx
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%define arg2 arg2_m
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%define arg2_m arg(2)
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%define arg3 trans
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%define arg3_m arg(3)
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%define arg4 trans
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%define arg4_m arg(4)
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%define tmp edx
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%define tmp2 edi
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%define tmp3 trans2
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%define tmp4 trans2
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%define tmp4_m var(0)
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%define return eax
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%macro SLDR 2 ;; stack load/restore
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mov %1, %2
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%endmacro
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%define SSTR SLDR
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%macro FUNC_SAVE 0
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push ebp
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mov ebp, esp
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sub esp, PS*1 ;1 local variable
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push esi
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push edi
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push ebx
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mov arg1, arg(1)
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%endmacro
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%macro FUNC_RESTORE 0
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pop ebx
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pop edi
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pop esi
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add esp, PS*1 ;1 local variable
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pop ebp
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%endmacro
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%endif ; output formats
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%define len arg0
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%define vec arg1
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%define mul_array arg2
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%define src arg3
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%define dest1 arg4
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%define vec_i tmp2
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%define ptr tmp3
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%define dest2 tmp4
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%define pos return
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%ifidn PS,4 ;32-bit code
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%define len_m arg0_m
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%define src_m arg3_m
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%define dest1_m arg4_m
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%define dest2_m tmp4_m
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%endif
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%ifndef EC_ALIGNED_ADDR
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;;; Use Un-aligned load/store
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%define XLDR vmovdqu
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%define XSTR vmovdqu
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%else
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;;; Use Non-temporal load/stor
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%ifdef NO_NT_LDST
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%define XLDR vmovdqa
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%define XSTR vmovdqa
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%else
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%define XLDR vmovntdqa
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%define XSTR vmovntdq
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%endif
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%endif
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%ifidn PS,8 ; 64-bit code
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default rel
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[bits 64]
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%endif
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section .text
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%ifidn PS,8 ;64-bit code
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%define xmask0f xmm8
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%define xgft1_lo xmm7
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%define xgft1_hi xmm6
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%define xgft2_lo xmm5
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%define xgft2_hi xmm4
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%define x0 xmm0
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%define xtmpa xmm1
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%define xp1 xmm2
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%define xp2 xmm3
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%else ;32-bit code
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%define xmask0f xmm4
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%define xgft1_lo xmm7
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%define xgft1_hi xmm6
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%define xgft2_lo xgft1_lo
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%define xgft2_hi xgft1_hi
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%define x0 xmm0
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%define xtmpa xmm1
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%define xp1 xmm2
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%define xp2 xmm3
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%endif
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align 16
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global gf_2vect_dot_prod_avx:function
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func(gf_2vect_dot_prod_avx)
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FUNC_SAVE
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SLDR len, len_m
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sub len, 16
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SSTR len_m, len
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jl .return_fail
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xor pos, pos
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vmovdqa xmask0f, [mask0f] ;Load mask of lower nibble in each byte
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sal vec, LOG_PS ;vec *= PS. Make vec_i count by PS
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SLDR dest1, dest1_m
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mov dest2, [dest1+PS]
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SSTR dest2_m, dest2
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mov dest1, [dest1]
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SSTR dest1_m, dest1
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.loop16:
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vpxor xp1, xp1
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vpxor xp2, xp2
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mov tmp, mul_array
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xor vec_i, vec_i
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.next_vect:
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SLDR src, src_m
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mov ptr, [src+vec_i]
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vmovdqu xgft1_lo, [tmp] ;Load array Ax{00}, Ax{01}, ..., Ax{0f}
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vmovdqu xgft1_hi, [tmp+16] ; " Ax{00}, Ax{10}, ..., Ax{f0}
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%ifidn PS,8 ; 64-bit code
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vmovdqu xgft2_lo, [tmp+vec*(32/PS)] ;Load array Bx{00}, Bx{01}, ..., Bx{0f}
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vmovdqu xgft2_hi, [tmp+vec*(32/PS)+16] ; " Bx{00}, Bx{10}, ..., Bx{f0}
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add tmp, 32
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add vec_i, PS
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%endif
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XLDR x0, [ptr+pos] ;Get next source vector
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vpand xtmpa, x0, xmask0f ;Mask low src nibble in bits 4-0
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vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
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vpand x0, x0, xmask0f ;Mask high src nibble in bits 4-0
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vpshufb xgft1_hi, x0 ;Lookup mul table of high nibble
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vpshufb xgft1_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xgft1_hi, xgft1_lo ;GF add high and low partials
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vpxor xp1, xgft1_hi ;xp1 += partial
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%ifidn PS,4 ; 32-bit code
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vmovdqu xgft2_lo, [tmp+vec*(32/PS)] ;Load array Bx{00}, Bx{01}, ..., Bx{0f}
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vmovdqu xgft2_hi, [tmp+vec*(32/PS)+16] ; " Bx{00}, Bx{10}, ..., Bx{f0}
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add tmp, 32
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add vec_i, PS
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%endif
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vpshufb xgft2_hi, x0 ;Lookup mul table of high nibble
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vpshufb xgft2_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xgft2_hi, xgft2_lo ;GF add high and low partials
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vpxor xp2, xgft2_hi ;xp2 += partial
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cmp vec_i, vec
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jl .next_vect
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SLDR dest1, dest1_m
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SLDR dest2, dest2_m
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XSTR [dest1+pos], xp1
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XSTR [dest2+pos], xp2
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SLDR len, len_m
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add pos, 16 ;Loop on 16 bytes at a time
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cmp pos, len
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jle .loop16
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lea tmp, [len + 16]
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cmp pos, tmp
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je .return_pass
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;; Tail len
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mov pos, len ;Overlapped offset length-16
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jmp .loop16 ;Do one more overlap pass
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.return_pass:
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mov return, 0
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FUNC_RESTORE
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ret
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.return_fail:
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mov return, 1
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FUNC_RESTORE
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ret
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endproc_frame
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section .data
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align 16
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mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
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;;; func core, ver, snum
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slversion gf_2vect_dot_prod_avx, 02, 05, 0191
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