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cd888f01a4
To support Intel CET, all indirect branch targets must start with ENDBR32/ENDBR64. Here is a patch to define endbranch and add it to function entries in x86 assembly codes which are indirect branch targets as discovered by running testsuite on Intel CET machine and visual inspection. Verified with $ CC="gcc -Wl,-z,cet-report=error -fcf-protection" CXX="g++ -Wl,-z,cet-report=error -fcf-protection" .../configure x86_64-linux $ make -j8 $ make -j8 check with both nasm and yasm on both CET and non-CET machines. Change-Id: I9822578e7294fb5043a64ab7de5c41de81a7d337 Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
327 lines
9.1 KiB
NASM
327 lines
9.1 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; gf_6vect_dot_prod_avx2(len, vec, *g_tbls, **buffs, **dests);
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;;;
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%include "reg_sizes.asm"
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%ifidn __OUTPUT_FORMAT__, elf64
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%define arg0 rdi
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%define arg1 rsi
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%define arg2 rdx
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%define arg3 rcx
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%define arg4 r8
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%define arg5 r9
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%define tmp r11
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%define tmp.w r11d
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%define tmp.b r11b
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%define tmp2 r10
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%define tmp3 r13 ; must be saved and restored
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%define tmp4 r12 ; must be saved and restored
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%define tmp5 r14 ; must be saved and restored
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%define tmp6 r15 ; must be saved and restored
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%define return rax
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%define PS 8
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%define LOG_PS 3
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%define func(x) x: endbranch
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%macro FUNC_SAVE 0
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push r12
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push r13
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push r14
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push r15
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%endmacro
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%macro FUNC_RESTORE 0
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pop r15
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pop r14
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pop r13
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pop r12
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%endmacro
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%endif
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%ifidn __OUTPUT_FORMAT__, win64
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%define arg0 rcx
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%define arg1 rdx
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%define arg2 r8
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%define arg3 r9
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%define arg4 r12 ; must be saved, loaded and restored
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%define arg5 r15 ; must be saved and restored
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%define tmp r11
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%define tmp.w r11d
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%define tmp.b r11b
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%define tmp2 r10
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%define tmp3 r13 ; must be saved and restored
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%define tmp4 r14 ; must be saved and restored
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%define tmp5 rdi ; must be saved and restored
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%define tmp6 rsi ; must be saved and restored
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%define return rax
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%define PS 8
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%define LOG_PS 3
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%define stack_size 10*16 + 7*8 ; must be an odd multiple of 8
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%define arg(x) [rsp + stack_size + PS + PS*x]
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%define func(x) proc_frame x
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%macro FUNC_SAVE 0
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alloc_stack stack_size
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vmovdqa [rsp + 0*16], xmm6
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vmovdqa [rsp + 1*16], xmm7
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vmovdqa [rsp + 2*16], xmm8
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vmovdqa [rsp + 3*16], xmm9
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vmovdqa [rsp + 4*16], xmm10
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vmovdqa [rsp + 5*16], xmm11
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vmovdqa [rsp + 6*16], xmm12
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vmovdqa [rsp + 7*16], xmm13
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vmovdqa [rsp + 8*16], xmm14
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vmovdqa [rsp + 9*16], xmm15
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save_reg r12, 10*16 + 0*8
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save_reg r13, 10*16 + 1*8
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save_reg r14, 10*16 + 2*8
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save_reg r15, 10*16 + 3*8
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save_reg rdi, 10*16 + 4*8
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save_reg rsi, 10*16 + 5*8
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end_prolog
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mov arg4, arg(4)
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%endmacro
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%macro FUNC_RESTORE 0
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vmovdqa xmm6, [rsp + 0*16]
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vmovdqa xmm7, [rsp + 1*16]
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vmovdqa xmm8, [rsp + 2*16]
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vmovdqa xmm9, [rsp + 3*16]
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vmovdqa xmm10, [rsp + 4*16]
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vmovdqa xmm11, [rsp + 5*16]
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vmovdqa xmm12, [rsp + 6*16]
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vmovdqa xmm13, [rsp + 7*16]
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vmovdqa xmm14, [rsp + 8*16]
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vmovdqa xmm15, [rsp + 9*16]
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mov r12, [rsp + 10*16 + 0*8]
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mov r13, [rsp + 10*16 + 1*8]
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mov r14, [rsp + 10*16 + 2*8]
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mov r15, [rsp + 10*16 + 3*8]
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mov rdi, [rsp + 10*16 + 4*8]
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mov rsi, [rsp + 10*16 + 5*8]
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add rsp, stack_size
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%endmacro
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%endif
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%define len arg0
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%define vec arg1
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%define mul_array arg2
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%define src arg3
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%define dest arg4
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%define ptr arg5
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%define vec_i tmp2
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%define dest1 tmp3
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%define dest2 tmp4
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%define vskip1 tmp5
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%define vskip3 tmp6
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%define pos return
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%ifndef EC_ALIGNED_ADDR
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;;; Use Un-aligned load/store
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%define XLDR vmovdqu
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%define XSTR vmovdqu
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%else
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;;; Use Non-temporal load/stor
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%ifdef NO_NT_LDST
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%define XLDR vmovdqa
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%define XSTR vmovdqa
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%else
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%define XLDR vmovntdqa
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%define XSTR vmovntdq
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%endif
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%endif
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default rel
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[bits 64]
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section .text
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%define xmask0f ymm15
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%define xmask0fx xmm15
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%define xgft1_lo ymm14
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%define xgft1_hi ymm13
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%define xgft2_lo ymm12
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%define xgft2_hi ymm11
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%define xgft3_lo ymm10
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%define xgft3_hi ymm9
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%define x0 ymm0
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%define xtmpa ymm1
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%define xp1 ymm2
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%define xp2 ymm3
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%define xp3 ymm4
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%define xp4 ymm5
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%define xp5 ymm6
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%define xp6 ymm7
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align 16
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mk_global gf_6vect_dot_prod_avx2, function
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func(gf_6vect_dot_prod_avx2)
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FUNC_SAVE
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sub len, 32
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jl .return_fail
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xor pos, pos
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mov tmp.b, 0x0f
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vpinsrb xmask0fx, xmask0fx, tmp.w, 0
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vpbroadcastb xmask0f, xmask0fx ;Construct mask 0x0f0f0f...
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mov vskip1, vec
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imul vskip1, 32
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mov vskip3, vec
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imul vskip3, 96
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sal vec, LOG_PS ;vec *= PS. Make vec_i count by PS
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mov dest1, [dest]
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mov dest2, [dest+PS]
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.loop32:
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mov tmp, mul_array
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xor vec_i, vec_i
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vpxor xp1, xp1
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vpxor xp2, xp2
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vpxor xp3, xp3
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vpxor xp4, xp4
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vpxor xp5, xp5
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vpxor xp6, xp6
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.next_vect:
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mov ptr, [src+vec_i]
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XLDR x0, [ptr+pos] ;Get next source vector
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add vec_i, PS
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vpand xgft3_lo, x0, xmask0f ;Mask low src nibble in bits 4-0
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vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
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vpand x0, x0, xmask0f ;Mask high src nibble in bits 4-0
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vperm2i128 xtmpa, xgft3_lo, x0, 0x30 ;swap xtmpa from 1lo|2lo to 1lo|2hi
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vperm2i128 x0, xgft3_lo, x0, 0x12 ;swap x0 from 1hi|2hi to 1hi|2lo
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vmovdqu xgft1_lo, [tmp] ;Load array Ax{00}, Ax{01}, ..., Ax{0f}
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; " Ax{00}, Ax{10}, ..., Ax{f0}
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vmovdqu xgft2_lo, [tmp+vskip1*1] ;Load array Bx{00}, Bx{01}, ..., Bx{0f}
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; " Bx{00}, Bx{10}, ..., Bx{f0}
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vmovdqu xgft3_lo, [tmp+vskip1*2] ;Load array Cx{00}, Cx{01}, ..., Cx{0f}
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; " Cx{00}, Cx{10}, ..., Cx{f0}
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lea ptr, [vskip1 + vskip1*4] ;ptr = vskip5
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vperm2i128 xgft1_hi, xgft1_lo, xgft1_lo, 0x01 ; swapped to hi | lo
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vperm2i128 xgft2_hi, xgft2_lo, xgft2_lo, 0x01 ; swapped to hi | lo
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vperm2i128 xgft3_hi, xgft3_lo, xgft3_lo, 0x01 ; swapped to hi | lo
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vpshufb xgft1_hi, x0 ;Lookup mul table of high nibble
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vpshufb xgft1_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xgft1_hi, xgft1_lo ;GF add high and low partials
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vpxor xp1, xgft1_hi ;xp1 += partial
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vpshufb xgft2_hi, x0 ;Lookup mul table of high nibble
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vpshufb xgft2_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xgft2_hi, xgft2_lo ;GF add high and low partials
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vpxor xp2, xgft2_hi ;xp2 += partial
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vpshufb xgft3_hi, x0 ;Lookup mul table of high nibble
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vpshufb xgft3_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xgft3_hi, xgft3_lo ;GF add high and low partials
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vpxor xp3, xgft3_hi ;xp3 += partial
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vmovdqu xgft1_lo, [tmp+vskip3] ;Load array Dx{00}, Dx{01}, ..., Dx{0f}
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; " Dx{00}, Dx{10}, ..., Dx{f0}
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vmovdqu xgft2_lo, [tmp+vskip1*4] ;Load array Ex{00}, Ex{01}, ..., Ex{0f}
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; " Ex{00}, Ex{10}, ..., Ex{f0}
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vmovdqu xgft3_lo, [tmp+ptr] ;Load array Fx{00}, Fx{01}, ..., Fx{0f}
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; " Fx{00}, Fx{10}, ..., Fx{f0}
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add tmp, 32
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vperm2i128 xgft1_hi, xgft1_lo, xgft1_lo, 0x01 ; swapped to hi | lo
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vperm2i128 xgft2_hi, xgft2_lo, xgft2_lo, 0x01 ; swapped to hi | lo
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vperm2i128 xgft3_hi, xgft3_lo, xgft3_lo, 0x01 ; swapped to hi | lo
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vpshufb xgft1_hi, x0 ;Lookup mul table of high nibble
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vpshufb xgft1_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xgft1_hi, xgft1_lo ;GF add high and low partials
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vpxor xp4, xgft1_hi ;xp4 += partial
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vpshufb xgft2_hi, x0 ;Lookup mul table of high nibble
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vpshufb xgft2_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xgft2_hi, xgft2_lo ;GF add high and low partials
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vpxor xp5, xgft2_hi ;xp5 += partial
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vpshufb xgft3_hi, x0 ;Lookup mul table of high nibble
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vpshufb xgft3_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xgft3_hi, xgft3_lo ;GF add high and low partials
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vpxor xp6, xgft3_hi ;xp6 += partial
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cmp vec_i, vec
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jl .next_vect
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mov tmp, [dest+2*PS]
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mov ptr, [dest+3*PS]
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mov vec_i, [dest+4*PS]
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XSTR [dest1+pos], xp1
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XSTR [dest2+pos], xp2
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XSTR [tmp+pos], xp3
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mov tmp, [dest+5*PS]
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XSTR [ptr+pos], xp4
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XSTR [vec_i+pos], xp5
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XSTR [tmp+pos], xp6
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add pos, 32 ;Loop on 32 bytes at a time
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cmp pos, len
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jle .loop32
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lea tmp, [len + 32]
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cmp pos, tmp
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je .return_pass
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;; Tail len
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mov pos, len ;Overlapped offset length-16
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jmp .loop32 ;Do one more overlap pass
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.return_pass:
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FUNC_RESTORE
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mov return, 0
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ret
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.return_fail:
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FUNC_RESTORE
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mov return, 1
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ret
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endproc_frame
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section .data
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;;; func core, ver, snum
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slversion gf_6vect_dot_prod_avx2, 04, 04, 019a
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