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cd888f01a4
To support Intel CET, all indirect branch targets must start with ENDBR32/ENDBR64. Here is a patch to define endbranch and add it to function entries in x86 assembly codes which are indirect branch targets as discovered by running testsuite on Intel CET machine and visual inspection. Verified with $ CC="gcc -Wl,-z,cet-report=error -fcf-protection" CXX="g++ -Wl,-z,cet-report=error -fcf-protection" .../configure x86_64-linux $ make -j8 $ make -j8 check with both nasm and yasm on both CET and non-CET machines. Change-Id: I9822578e7294fb5043a64ab7de5c41de81a7d337 Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
600 lines
14 KiB
NASM
600 lines
14 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2017 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Function API:
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; UINT16 crc16_t10dif_copy_by4(
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; UINT16 init_crc, //initial CRC value, 16 bits
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; unsigned char *dst, //buffer pointer destination for copy
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; const unsigned char *src, //buffer pointer to calculate CRC on
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; UINT64 len //buffer length in bytes (64-bit data)
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; );
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;
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; Authors:
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; Erdinc Ozturk
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; Vinodh Gopal
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; James Guilford
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;
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; Reference paper titled "Fast CRC Computation for Generic Polynomials Using PCLMULQDQ Instruction"
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; URL: http://download.intel.com/design/intarch/papers/323102.pdf
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;
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%include "reg_sizes.asm"
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%define fetch_dist 1024
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[bits 64]
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default rel
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section .text
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%ifidn __OUTPUT_FORMAT__, win64
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%xdefine arg1 rcx
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%xdefine arg2 rdx
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%xdefine arg3 r8
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%xdefine arg4 r9
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%xdefine tmp1 r10
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%xdefine arg1_low32 ecx
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%else
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%xdefine arg1 rdi
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%xdefine arg2 rsi
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%xdefine arg3 rdx
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%xdefine arg4 rcx
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%xdefine tmp1 r10
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%xdefine arg1_low32 edi
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%endif
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align 16
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mk_global crc16_t10dif_copy_by4, function
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crc16_t10dif_copy_by4:
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endbranch
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; adjust the 16-bit initial_crc value, scale it to 32 bits
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shl arg1_low32, 16
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; After this point, code flow is exactly same as a 32-bit CRC.
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; The only difference is before returning eax, we will shift
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; it right 16 bits, to scale back to 16 bits.
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sub rsp,16*4+8
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; push the xmm registers into the stack to maintain
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movdqa [rsp+16*2],xmm6
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movdqa [rsp+16*3],xmm7
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; check if smaller than 128B
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cmp arg4, 128
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; for sizes less than 128, we can't fold 64B at a time...
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jl _less_than_128
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; load the initial crc value
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movd xmm6, arg1_low32 ; initial crc
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; crc value does not need to be byte-reflected, but it needs to
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; be moved to the high part of the register.
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; because data will be byte-reflected and will align with
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; initial crc at correct place.
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pslldq xmm6, 12
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movdqa xmm7, [SHUF_MASK]
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; receive the initial 64B data, xor the initial crc value
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movdqu xmm0, [arg3]
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movdqu xmm1, [arg3+16]
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movdqu xmm2, [arg3+32]
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movdqu xmm3, [arg3+48]
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; copy initial data
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movdqu [arg2], xmm0
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movdqu [arg2+16], xmm1
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movdqu [arg2+32], xmm2
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movdqu [arg2+48], xmm3
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pshufb xmm0, xmm7
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; XOR the initial_crc value
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pxor xmm0, xmm6
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pshufb xmm1, xmm7
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pshufb xmm2, xmm7
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pshufb xmm3, xmm7
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movdqa xmm6, [rk3] ;xmm6 has rk3 and rk4
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;imm value of pclmulqdq instruction
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;will determine which constant to use
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; we subtract 128 instead of 64 to save one instruction from the loop
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sub arg4, 128
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; at this section of the code, there is 64*x+y (0<=y<64) bytes of
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; buffer. The _fold_64_B_loop
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; loop will fold 64B at a time until we have 64+y Bytes of buffer
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; fold 64B at a time. This section of the code folds 4 xmm
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; registers in parallel
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_fold_64_B_loop:
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; update the buffer pointer
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add arg3, 64 ; buf += 64;
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add arg2, 64
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prefetchnta [arg3+fetch_dist+0]
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movdqu xmm4, xmm0
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movdqu xmm5, xmm1
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pclmulqdq xmm0, xmm6 , 0x11
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pclmulqdq xmm1, xmm6 , 0x11
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pclmulqdq xmm4, xmm6, 0x0
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pclmulqdq xmm5, xmm6, 0x0
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pxor xmm0, xmm4
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pxor xmm1, xmm5
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prefetchnta [arg3+fetch_dist+32]
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movdqu xmm4, xmm2
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movdqu xmm5, xmm3
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pclmulqdq xmm2, xmm6, 0x11
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pclmulqdq xmm3, xmm6, 0x11
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pclmulqdq xmm4, xmm6, 0x0
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pclmulqdq xmm5, xmm6, 0x0
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pxor xmm2, xmm4
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pxor xmm3, xmm5
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movdqu xmm4, [arg3]
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movdqu xmm5, [arg3+16]
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movdqu [arg2], xmm4
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movdqu [arg2+16], xmm5
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pshufb xmm4, xmm7
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pshufb xmm5, xmm7
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pxor xmm0, xmm4
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pxor xmm1, xmm5
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movdqu xmm4, [arg3+32]
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movdqu xmm5, [arg3+48]
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movdqu [arg2+32], xmm4
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movdqu [arg2+48], xmm5
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pshufb xmm4, xmm7
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pshufb xmm5, xmm7
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pxor xmm2, xmm4
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pxor xmm3, xmm5
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sub arg4, 64
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; check if there is another 64B in the buffer to be able to fold
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jge _fold_64_B_loop
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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add arg3, 64
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add arg2, 64
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; at this point, the buffer pointer is pointing at the last y Bytes of the buffer
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; the 64B of folded data is in 4 of the xmm registers: xmm0, xmm1, xmm2, xmm3
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; fold the 4 xmm registers to 1 xmm register with different constants
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movdqa xmm6, [rk1] ;xmm6 has rk1 and rk2
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;imm value of pclmulqdq instruction will
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;determine which constant to use
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movdqa xmm4, xmm0
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pclmulqdq xmm0, xmm6, 0x11
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pclmulqdq xmm4, xmm6, 0x0
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pxor xmm1, xmm4
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pxor xmm1, xmm0
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movdqa xmm4, xmm1
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pclmulqdq xmm1, xmm6, 0x11
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pclmulqdq xmm4, xmm6, 0x0
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pxor xmm2, xmm4
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pxor xmm2, xmm1
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movdqa xmm4, xmm2
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pclmulqdq xmm2, xmm6, 0x11
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pclmulqdq xmm4, xmm6, 0x0
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pxor xmm3, xmm4
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pxor xmm3, xmm2
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; instead of 64, we add 48 to the loop counter to save 1 instruction from the loop
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; instead of a cmp instruction, we use the negative flag with the jl instruction
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add arg4, 64-16
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jl _final_reduction_for_128
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; now we have 16+y bytes left to reduce. 16 Bytes
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; is in register xmm3 and the rest is in memory
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; we can fold 16 bytes at a time if y>=16
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; continue folding 16B at a time
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_16B_reduction_loop:
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movdqa xmm4, xmm3
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pclmulqdq xmm3, xmm6, 0x11
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pclmulqdq xmm4, xmm6, 0x0
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pxor xmm3, xmm4
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movdqu xmm0, [arg3]
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movdqu [arg2], xmm0
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pshufb xmm0, xmm7
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pxor xmm3, xmm0
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add arg3, 16
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add arg2, 16
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sub arg4, 16
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; instead of a cmp instruction, we utilize the flags with the jge instruction
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; equivalent of: cmp arg4, 16-16
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; check if there is any more 16B in the buffer to be able to fold
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jge _16B_reduction_loop
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;now we have 16+z bytes left to reduce, where 0<= z < 16.
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;first, we reduce the data in the xmm3 register
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_final_reduction_for_128:
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; check if any more data to fold. If not, compute the CRC of the final 128 bits
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add arg4, 16
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je _128_done
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; here we are getting data that is less than 16 bytes.
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; since we know that there was data before the pointer,
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; we can offset the input pointer before the actual point,
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; to receive exactly 16 bytes.
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; after that the registers need to be adjusted.
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_get_last_two_xmms:
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movdqa xmm2, xmm3
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movdqu xmm1, [arg3 - 16 + arg4]
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movdqu [arg2 - 16 + arg4], xmm1
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pshufb xmm1, xmm7
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; get rid of the extra data that was loaded before
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; load the shift constant
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lea rax, [pshufb_shf_table + 16]
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sub rax, arg4
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movdqu xmm0, [rax]
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; shift xmm2 to the left by arg4 bytes
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pshufb xmm2, xmm0
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; shift xmm3 to the right by 16-arg4 bytes
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pxor xmm0, [mask1]
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pshufb xmm3, xmm0
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pblendvb xmm1, xmm2 ;xmm0 is implicit
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; fold 16 Bytes
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movdqa xmm2, xmm1
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movdqa xmm4, xmm3
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pclmulqdq xmm3, xmm6, 0x11
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pclmulqdq xmm4, xmm6, 0x0
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pxor xmm3, xmm4
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pxor xmm3, xmm2
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_128_done:
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; compute crc of a 128-bit value
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movdqa xmm6, [rk5] ; rk5 and rk6 in xmm6
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movdqa xmm0, xmm3
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;64b fold
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pclmulqdq xmm3, xmm6, 0x1
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pslldq xmm0, 8
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pxor xmm3, xmm0
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;32b fold
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movdqa xmm0, xmm3
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pand xmm0, [mask2]
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psrldq xmm3, 12
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pclmulqdq xmm3, xmm6, 0x10
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pxor xmm3, xmm0
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;barrett reduction
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_barrett:
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movdqa xmm6, [rk7] ; rk7 and rk8 in xmm6
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movdqa xmm0, xmm3
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pclmulqdq xmm3, xmm6, 0x01
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pslldq xmm3, 4
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pclmulqdq xmm3, xmm6, 0x11
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pslldq xmm3, 4
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pxor xmm3, xmm0
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pextrd eax, xmm3,1
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_cleanup:
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; scale the result back to 16 bits
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shr eax, 16
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movdqa xmm6, [rsp+16*2]
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movdqa xmm7, [rsp+16*3]
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add rsp,16*4+8
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ret
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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align 16
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_less_than_128:
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; check if there is enough buffer to be able to fold 16B at a time
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cmp arg4, 32
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jl _less_than_32
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movdqa xmm7, [SHUF_MASK]
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; if there is, load the constants
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movdqa xmm6, [rk1] ; rk1 and rk2 in xmm6
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movd xmm0, arg1_low32 ; get the initial crc value
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pslldq xmm0, 12 ; align it to its correct place
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movdqu xmm3, [arg3] ; load the plaintext
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movdqu [arg2], xmm3 ; store copy
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pshufb xmm3, xmm7 ; byte-reflect the plaintext
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pxor xmm3, xmm0
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; update the buffer pointer
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add arg3, 16
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add arg2, 16
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; update the counter. subtract 32 instead of 16 to save one instruction from the loop
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sub arg4, 32
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jmp _16B_reduction_loop
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align 16
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_less_than_32:
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; mov initial crc to the return value. this is necessary for zero-length buffers.
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mov eax, arg1_low32
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test arg4, arg4
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je _cleanup
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movdqa xmm7, [SHUF_MASK]
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movd xmm0, arg1_low32 ; get the initial crc value
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pslldq xmm0, 12 ; align it to its correct place
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cmp arg4, 16
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je _exact_16_left
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jl _less_than_16_left
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movdqu xmm3, [arg3] ; load the plaintext
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movdqu [arg2], xmm3 ; store the copy
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pshufb xmm3, xmm7 ; byte-reflect the plaintext
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pxor xmm3, xmm0 ; xor the initial crc value
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add arg3, 16
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add arg2, 16
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sub arg4, 16
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movdqa xmm6, [rk1] ; rk1 and rk2 in xmm6
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jmp _get_last_two_xmms
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align 16
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_less_than_16_left:
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; use stack space to load data less than 16 bytes, zero-out the 16B in memory first.
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pxor xmm1, xmm1
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mov r11, rsp
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movdqa [r11], xmm1
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cmp arg4, 4
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jl _only_less_than_4
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; backup the counter value
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mov tmp1, arg4
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cmp arg4, 8
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jl _less_than_8_left
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; load 8 Bytes
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mov rax, [arg3]
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mov [arg2], rax
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mov [r11], rax
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add r11, 8
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sub arg4, 8
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add arg3, 8
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add arg2, 8
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_less_than_8_left:
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cmp arg4, 4
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jl _less_than_4_left
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; load 4 Bytes
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mov eax, [arg3]
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mov [arg2], eax
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mov [r11], eax
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add r11, 4
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sub arg4, 4
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add arg3, 4
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add arg2, 4
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_less_than_4_left:
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cmp arg4, 2
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jl _less_than_2_left
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; load 2 Bytes
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mov ax, [arg3]
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mov [arg2], ax
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mov [r11], ax
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add r11, 2
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sub arg4, 2
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add arg3, 2
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add arg2, 2
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_less_than_2_left:
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cmp arg4, 1
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jl _zero_left
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; load 1 Byte
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mov al, [arg3]
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mov [arg2], al
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mov [r11], al
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_zero_left:
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movdqa xmm3, [rsp]
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pshufb xmm3, xmm7
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pxor xmm3, xmm0 ; xor the initial crc value
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; shl tmp1, 4
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lea rax, [pshufb_shf_table + 16]
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sub rax, tmp1
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movdqu xmm0, [rax]
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pxor xmm0, [mask1]
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pshufb xmm3, xmm0
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jmp _128_done
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align 16
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_exact_16_left:
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movdqu xmm3, [arg3]
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movdqu [arg2], xmm3
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pshufb xmm3, xmm7
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pxor xmm3, xmm0 ; xor the initial crc value
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jmp _128_done
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_only_less_than_4:
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cmp arg4, 3
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jl _only_less_than_3
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; load 3 Bytes
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mov al, [arg3]
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mov [arg2], al
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mov [r11], al
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mov al, [arg3+1]
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mov [arg2+1], al
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mov [r11+1], al
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mov al, [arg3+2]
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mov [arg2+2], al
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mov [r11+2], al
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movdqa xmm3, [rsp]
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pshufb xmm3, xmm7
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pxor xmm3, xmm0 ; xor the initial crc value
|
|
|
|
psrldq xmm3, 5
|
|
|
|
jmp _barrett
|
|
_only_less_than_3:
|
|
cmp arg4, 2
|
|
jl _only_less_than_2
|
|
|
|
; load 2 Bytes
|
|
mov al, [arg3]
|
|
mov [arg2], al
|
|
mov [r11], al
|
|
|
|
mov al, [arg3+1]
|
|
mov [arg2+1], al
|
|
mov [r11+1], al
|
|
|
|
movdqa xmm3, [rsp]
|
|
pshufb xmm3, xmm7
|
|
pxor xmm3, xmm0 ; xor the initial crc value
|
|
|
|
psrldq xmm3, 6
|
|
|
|
jmp _barrett
|
|
_only_less_than_2:
|
|
|
|
; load 1 Byte
|
|
mov al, [arg3]
|
|
mov [arg2],al
|
|
mov [r11], al
|
|
|
|
movdqa xmm3, [rsp]
|
|
pshufb xmm3, xmm7
|
|
pxor xmm3, xmm0 ; xor the initial crc value
|
|
|
|
psrldq xmm3, 7
|
|
|
|
jmp _barrett
|
|
|
|
section .data
|
|
|
|
; precomputed constants
|
|
; these constants are precomputed from the poly: 0x8bb70000 (0x8bb7 scaled to 32 bits)
|
|
align 16
|
|
; Q = 0x18BB70000
|
|
; rk1 = 2^(32*3) mod Q << 32
|
|
; rk2 = 2^(32*5) mod Q << 32
|
|
; rk3 = 2^(32*15) mod Q << 32
|
|
; rk4 = 2^(32*17) mod Q << 32
|
|
; rk5 = 2^(32*3) mod Q << 32
|
|
; rk6 = 2^(32*2) mod Q << 32
|
|
; rk7 = floor(2^64/Q)
|
|
; rk8 = Q
|
|
rk1:
|
|
DQ 0x2d56000000000000
|
|
rk2:
|
|
DQ 0x06df000000000000
|
|
rk3:
|
|
DQ 0x044c000000000000
|
|
rk4:
|
|
DQ 0xe658000000000000
|
|
rk5:
|
|
DQ 0x2d56000000000000
|
|
rk6:
|
|
DQ 0x1368000000000000
|
|
rk7:
|
|
DQ 0x00000001f65a57f8
|
|
rk8:
|
|
DQ 0x000000018bb70000
|
|
mask1:
|
|
dq 0x8080808080808080, 0x8080808080808080
|
|
mask2:
|
|
dq 0xFFFFFFFFFFFFFFFF, 0x00000000FFFFFFFF
|
|
|
|
SHUF_MASK:
|
|
dq 0x08090A0B0C0D0E0F, 0x0001020304050607
|
|
|
|
pshufb_shf_table:
|
|
; use these values for shift constants for the pshufb instruction
|
|
; different alignments result in values as shown:
|
|
; dq 0x8887868584838281, 0x008f8e8d8c8b8a89 ; shl 15 (16-1) / shr1
|
|
; dq 0x8988878685848382, 0x01008f8e8d8c8b8a ; shl 14 (16-3) / shr2
|
|
; dq 0x8a89888786858483, 0x0201008f8e8d8c8b ; shl 13 (16-4) / shr3
|
|
; dq 0x8b8a898887868584, 0x030201008f8e8d8c ; shl 12 (16-4) / shr4
|
|
; dq 0x8c8b8a8988878685, 0x04030201008f8e8d ; shl 11 (16-5) / shr5
|
|
; dq 0x8d8c8b8a89888786, 0x0504030201008f8e ; shl 10 (16-6) / shr6
|
|
; dq 0x8e8d8c8b8a898887, 0x060504030201008f ; shl 9 (16-7) / shr7
|
|
; dq 0x8f8e8d8c8b8a8988, 0x0706050403020100 ; shl 8 (16-8) / shr8
|
|
; dq 0x008f8e8d8c8b8a89, 0x0807060504030201 ; shl 7 (16-9) / shr9
|
|
; dq 0x01008f8e8d8c8b8a, 0x0908070605040302 ; shl 6 (16-10) / shr10
|
|
; dq 0x0201008f8e8d8c8b, 0x0a09080706050403 ; shl 5 (16-11) / shr11
|
|
; dq 0x030201008f8e8d8c, 0x0b0a090807060504 ; shl 4 (16-12) / shr12
|
|
; dq 0x04030201008f8e8d, 0x0c0b0a0908070605 ; shl 3 (16-13) / shr13
|
|
; dq 0x0504030201008f8e, 0x0d0c0b0a09080706 ; shl 2 (16-14) / shr14
|
|
; dq 0x060504030201008f, 0x0e0d0c0b0a090807 ; shl 1 (16-15) / shr15
|
|
dq 0x8786858483828100, 0x8f8e8d8c8b8a8988
|
|
dq 0x0706050403020100, 0x000e0d0c0b0a0908
|
|
|
|
;;; func core, ver, snum
|
|
slversion crc16_t10dif_copy_by4, 05, 02, 0000
|