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2e212f28fa
Change-Id: I9ee86a3e32876d3860477c8365fc459d94a8920e Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
241 lines
6.0 KiB
NASM
241 lines
6.0 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; gf_vect_dot_prod_avx512(len, vec, *g_tbls, **buffs, *dest);
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;;;
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%include "reg_sizes.asm"
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%ifdef HAVE_AS_KNOWS_AVX512
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%ifidn __OUTPUT_FORMAT__, elf64
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%define arg0 rdi
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%define arg1 rsi
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%define arg2 rdx
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%define arg3 rcx
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%define arg4 r8
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%define arg5 r9
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%define tmp r11
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%define tmp2 r10
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%define return rax
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%define PS 8
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%define LOG_PS 3
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%define func(x) x:
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%define FUNC_SAVE
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%define FUNC_RESTORE
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%endif
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%ifidn __OUTPUT_FORMAT__, win64
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%define arg0 rcx
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%define arg1 rdx
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%define arg2 r8
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%define arg3 r9
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%define arg4 r12 ; must be saved, loaded and restored
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%define arg5 r15 ; must be saved and restored
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%define tmp r11
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%define tmp2 r10
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%define return rax
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%define PS 8
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%define LOG_PS 3
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%define stack_size 0*16 + 3*8 ; must be an odd multiple of 8
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%define arg(x) [rsp + stack_size + PS + PS*x]
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%define func(x) proc_frame x
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%macro FUNC_SAVE 0
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alloc_stack stack_size
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save_reg r12, 9*16 + 0*8
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save_reg r15, 9*16 + 3*8
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end_prolog
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mov arg4, arg(4)
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%endmacro
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%macro FUNC_RESTORE 0
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mov r12, [rsp + 9*16 + 0*8]
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mov r15, [rsp + 9*16 + 3*8]
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add rsp, stack_size
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%endmacro
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%endif
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%define len arg0
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%define vec arg1
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%define mul_array arg2
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%define src arg3
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%define dest1 arg4
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%define ptr arg5
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%define vec_i tmp2
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%define pos return
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%ifndef EC_ALIGNED_ADDR
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;;; Use Un-aligned load/store
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%define XLDR vmovdqu8
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%define XSTR vmovdqu8
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%else
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;;; Use Non-temporal load/stor
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%ifdef NO_NT_LDST
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%define XLDR vmovdqa
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%define XSTR vmovdqa
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%else
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%define XLDR vmovntdqa
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%define XSTR vmovntdq
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%endif
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%endif
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%define xmask0f zmm5
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%define xgft1_lo zmm4
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%define xgft1_loy ymm4
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%define xgft1_hi zmm3
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%define x0 zmm0
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%define xgft1_loy ymm4
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%define x0y ymm0
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%define xtmpa zmm1
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%define xp1 zmm2
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%define xp1y ymm2
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default rel
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[bits 64]
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section .text
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align 16
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global gf_vect_dot_prod_avx512:ISAL_SYM_TYPE_FUNCTION
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func(gf_vect_dot_prod_avx512)
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FUNC_SAVE
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xor pos, pos
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mov tmp, 0x0f
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vpbroadcastb xmask0f, tmp ;Construct mask 0x0f0f0f...
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sal vec, LOG_PS ;vec *= PS. Make vec_i count by PS
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sub len, 64
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jl .len_lt_64
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.loop64:
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vpxorq xp1, xp1, xp1
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mov tmp, mul_array
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xor vec_i, vec_i
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.next_vect:
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mov ptr, [src+vec_i]
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XLDR x0, [ptr+pos] ;Get next source vector
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add vec_i, PS
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vpandq xtmpa, x0, xmask0f ;Mask low src nibble in bits 4-0
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vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
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vpandq x0, x0, xmask0f ;Mask high src nibble in bits 4-0
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vmovdqu8 xgft1_loy, [tmp] ;Load array Ax{00}..{0f}, Ax{00}..{f0}
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add tmp, 32
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vshufi64x2 xgft1_hi, xgft1_lo, xgft1_lo, 0x55
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vshufi64x2 xgft1_lo, xgft1_lo, xgft1_lo, 0x00
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vpshufb xgft1_hi, xgft1_hi, x0 ;Lookup mul table of high nibble
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vpshufb xgft1_lo, xgft1_lo, xtmpa ;Lookup mul table of low nibble
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vpxorq xgft1_hi, xgft1_hi, xgft1_lo ;GF add high and low partials
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vpxorq xp1, xp1, xgft1_hi ;xp1 += partial
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cmp vec_i, vec
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jl .next_vect
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XSTR [dest1+pos], xp1
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add pos, 64 ;Loop on 64 bytes at a time
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cmp pos, len
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jle .loop64
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lea tmp, [len + 64]
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cmp pos, tmp
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je .return_pass
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;; Tail len
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mov pos, len ;Overlapped offset length-64
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jmp .loop64 ;Do one more overlap pass
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.len_lt_64: ; 32-byte version
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add len, 32
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jl .return_fail
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.loop32:
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vpxorq xp1, xp1, xp1
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mov tmp, mul_array
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xor vec_i, vec_i
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.next_vect2:
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mov ptr, [src+vec_i]
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XLDR x0y, [ptr+pos] ;Get next source vector 32B
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add vec_i, PS
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vpsraw xtmpa, x0, 4 ;Shift to put high nibble into bits 4-0
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vshufi64x2 x0, x0, xtmpa, 0x44 ;put x0 = xl:xh
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vpandq x0, x0, xmask0f ;Mask bits 4-0
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vmovdqu8 xgft1_loy, [tmp] ;Load array Ax{00}..{0f}, Ax{00}..{f0}
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add tmp, 32
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vshufi64x2 xgft1_lo, xgft1_lo, xgft1_lo, 0x50 ;=AlAh:AlAh
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vpshufb xgft1_lo, xgft1_lo, x0 ;Lookup mul table
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vshufi64x2 xgft1_hi, xgft1_lo, xgft1_lo, 0x0e ;=xh:
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vpxorq xgft1_hi, xgft1_hi, xgft1_lo ;GF add high and low partials
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vpxorq xp1, xp1, xgft1_hi ;xp1 += partial
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cmp vec_i, vec
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jl .next_vect2
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XSTR [dest1+pos], xp1y
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add pos, 32 ;Loop on 32 bytes at a time
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cmp pos, len
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jle .loop32
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lea tmp, [len + 32]
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cmp pos, tmp
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je .return_pass
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;; Tail len
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mov pos, len ;Overlapped offset length-32
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jmp .loop32 ;Do one more overlap pass
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.return_pass:
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mov return, 0
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FUNC_RESTORE
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ret
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.return_fail:
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mov return, 1
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FUNC_RESTORE
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ret
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endproc_frame
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%else
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%ifidn __OUTPUT_FORMAT__, win64
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global no_gf_vect_dot_prod_avx512
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no_gf_vect_dot_prod_avx512:
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%endif
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%endif ; ifdef HAVE_AS_KNOWS_AVX512
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