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6c4d3dbf6c
To reduce the cache missing events, the mix layout is changed to PMULL+CRC. It also relaxes the final delay caused by data dependency. As results, the cold perf was improved about 20% and warm perf was improved about 4%. Change-Id: I7756f846edcb4f1665b4643a5a0e02283938cfdf Signed-off-by: Jerry Yu <jerry.h.yu@arm.com>
69 lines
2.5 KiB
ArmAsm
69 lines
2.5 KiB
ArmAsm
/**********************************************************************
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Copyright(c) 2020 Arm Corporation All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Arm Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**********************************************************************/
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.text
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.align 6
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.arch armv8-a+crypto+crc
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#include "crc32_common_mix_neoverse_n1.S"
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.Lconstants:
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.octa 0x000000009e4addf800000000740eef02
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.octa 0x000000014cd00bd600000000f20c0dfe
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.octa 0x00000000dea713f10000000105ec76f0
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.quad 0x00000000dd45aab8
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.quad 0x00000000FFFFFFFF
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.quad 0x000000009ef68d35
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.macro crc32_u64 dst,src,data
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crc32cx \dst,\src,\data
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.endm
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.macro crc32_u32 dst,src,data
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crc32cw \dst,\src,\data
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.endm
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.macro crc32_u16 dst,src,data
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crc32ch \dst,\src,\data
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.endm
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.macro crc32_u8 dst,src,data
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crc32cb \dst,\src,\data
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.endm
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/**
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* uint32_t crc32c_mix_neoverse_n1(uint8_t * BUF,
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* size_t LEN, uint CRC)
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*/
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BUF .req x0
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LEN .req x1
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CRC .req x2
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wCRC .req w2
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.align 6
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.global crc32c_mix_neoverse_n1
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.type crc32c_mix_neoverse_n1, %function
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crc32c_mix_neoverse_n1:
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crc32_common_mix crc32c
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.size crc32c_mix_neoverse_n1, .-crc32c_mix_neoverse_n1
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