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02a86dfb3f
Change-Id: I9fb9219c5f280ed88194ec63234af046a5a036ae Signed-off-by: Hang Li <lihang48@hisilicon.com>
456 lines
12 KiB
ArmAsm
456 lines
12 KiB
ArmAsm
/**************************************************************
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Copyright (c) 2019 Huawei Technologies Co., Ltd.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Huawei Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**********************************************************************/
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.text
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.global gf_4vect_mad_neon
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.type gf_4vect_mad_neon, %function
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/* arguments */
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x_len .req x0
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x_vec .req x1
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x_vec_i .req x2
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x_tbl .req x3
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x_src .req x4
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x_dest .req x5
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/* returns */
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w_ret .req w0
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/* local variables */
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x_src_end .req x6
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x_dest1 .req x7
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x_dest2 .req x8
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x_dest3 .req x9
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x_dest4 .req x_dest
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x_tmp .req x10
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x_tbl1 .req x11
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x_tbl2 .req x12
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x_tbl3 .req x13
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x_tbl4 .req x14
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x_const .req x15
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/* vectors */
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v_mask0f .req v0
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v_tmp_lo .req v1
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v_tmp_hi .req v2
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v_tmp .req v3
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q_tmp .req q3
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v_gft1_lo .req v4
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v_gft1_hi .req v5
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v_gft2_lo .req v6
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v_gft2_hi .req v7
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v_gft3_lo .req v16
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v_gft3_hi .req v17
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v_gft4_lo .req v18
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v_gft4_hi .req v19
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q_gft1_lo .req q4
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q_gft1_hi .req q5
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q_gft2_lo .req q6
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q_gft2_hi .req q7
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q_gft3_lo .req q16
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q_gft3_hi .req q17
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q_gft4_lo .req q18
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q_gft4_hi .req q19
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v_data_0 .req v8
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v_data_1 .req v9
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v_data_2 .req v10
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v_data_3 .req v11
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q_data_0 .req q8
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q_data_1 .req q9
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q_data_2 .req q10
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q_data_3 .req q11
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v_data_0_lo .req v12
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v_data_1_lo .req v13
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v_data_2_lo .req v14
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v_data_3_lo .req v15
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v_data_0_hi .req v_data_0
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v_data_1_hi .req v_data_1
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v_data_2_hi .req v_data_2
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v_data_3_hi .req v_data_3
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v_d1_0 .req v20
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v_d1_1 .req v21
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v_d1_2 .req v22
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v_d1_3 .req v23
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v_d2_0 .req v24
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v_d2_1 .req v25
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v_d2_2 .req v26
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v_d2_3 .req v27
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v_d3_0 .req v28
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v_d3_1 .req v29
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v_d3_2 .req v30
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v_d3_3 .req v31
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q_d1_0 .req q20
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q_d1_1 .req q21
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q_d1_2 .req q22
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q_d1_3 .req q23
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q_d2_0 .req q24
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q_d2_1 .req q25
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q_d2_2 .req q26
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q_d2_3 .req q27
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q_d3_0 .req q28
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q_d3_1 .req q29
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q_d3_2 .req q30
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q_d3_3 .req q31
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v_d4_0 .req v_d1_0
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v_d4_1 .req v_d1_1
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v_d4_2 .req v_d1_2
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v_d4_3 .req v_d1_3
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q_d4_0 .req q_d1_0
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q_d4_1 .req q_d1_1
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q_d4_2 .req q_d1_2
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q_d4_3 .req q_d1_3
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v_data .req v21
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q_data .req q21
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v_data_lo .req v22
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v_data_hi .req v23
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gf_4vect_mad_neon:
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/* less than 16 bytes, return_fail */
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cmp x_len, #16
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blt .return_fail
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movi v_mask0f.16b, #0x0f
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lsl x_vec_i, x_vec_i, #5
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lsl x_vec, x_vec, #5
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add x_tbl1, x_tbl, x_vec_i
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add x_tbl2, x_tbl1, x_vec
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add x_tbl3, x_tbl2, x_vec
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add x_tbl4, x_tbl3, x_vec
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add x_src_end, x_src, x_len
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ldr x_dest1, [x_dest, #8*0]
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ldr x_dest2, [x_dest, #8*1]
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ldr x_dest3, [x_dest, #8*2]
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ldr x_dest4, [x_dest, #8*3]
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ldr q_gft1_lo, [x_tbl1]
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ldr q_gft1_hi, [x_tbl1, #16]
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ldr q_gft2_lo, [x_tbl2]
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ldr q_gft2_hi, [x_tbl2, #16]
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ldr q_gft3_lo, [x_tbl3]
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ldr q_gft3_hi, [x_tbl3, #16]
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ldr q_gft4_lo, [x_tbl4]
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ldr q_gft4_hi, [x_tbl4, #16]
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.Lloop64_init:
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/* less than 64 bytes, goto Lloop16_init */
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cmp x_len, #64
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blt .Lloop16_init
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/* save d8 ~ d15 to stack */
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sub sp, sp, #64
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stp d8, d9, [sp]
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stp d10, d11, [sp, #16]
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stp d12, d13, [sp, #32]
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stp d14, d15, [sp, #48]
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sub x_src_end, x_src_end, #64
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.Lloop64:
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ldr q_data_0, [x_src, #16*0]
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ldr q_data_1, [x_src, #16*1]
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ldr q_data_2, [x_src, #16*2]
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ldr q_data_3, [x_src, #16*3]
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add x_src, x_src, #64
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ldr q_d1_0, [x_dest1, #16*0]
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ldr q_d1_1, [x_dest1, #16*1]
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ldr q_d1_2, [x_dest1, #16*2]
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ldr q_d1_3, [x_dest1, #16*3]
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ldr q_d2_0, [x_dest2, #16*0]
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ldr q_d2_1, [x_dest2, #16*1]
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ldr q_d2_2, [x_dest2, #16*2]
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ldr q_d2_3, [x_dest2, #16*3]
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and v_data_0_lo.16b, v_data_0.16b, v_mask0f.16b
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and v_data_1_lo.16b, v_data_1.16b, v_mask0f.16b
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and v_data_2_lo.16b, v_data_2.16b, v_mask0f.16b
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and v_data_3_lo.16b, v_data_3.16b, v_mask0f.16b
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ushr v_data_0_hi.16b, v_data_0.16b, #4
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ushr v_data_1_hi.16b, v_data_1.16b, #4
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ushr v_data_2_hi.16b, v_data_2.16b, #4
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ushr v_data_3_hi.16b, v_data_3.16b, #4
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/* dest1 */
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tbl v_tmp_lo.16b, {v_gft1_lo.16b}, v_data_0_lo.16b
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tbl v_tmp_hi.16b, {v_gft1_hi.16b}, v_data_0_hi.16b
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eor v_d1_0.16b, v_tmp_lo.16b, v_d1_0.16b
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eor v_d1_0.16b, v_d1_0.16b, v_tmp_hi.16b
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tbl v_tmp_lo.16b, {v_gft1_lo.16b}, v_data_1_lo.16b
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tbl v_tmp_hi.16b, {v_gft1_hi.16b}, v_data_1_hi.16b
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eor v_d1_1.16b, v_tmp_lo.16b, v_d1_1.16b
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eor v_d1_1.16b, v_d1_1.16b, v_tmp_hi.16b
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tbl v_tmp_lo.16b, {v_gft1_lo.16b}, v_data_2_lo.16b
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tbl v_tmp_hi.16b, {v_gft1_hi.16b}, v_data_2_hi.16b
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eor v_d1_2.16b, v_tmp_lo.16b, v_d1_2.16b
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eor v_d1_2.16b, v_d1_2.16b, v_tmp_hi.16b
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tbl v_tmp_lo.16b, {v_gft1_lo.16b}, v_data_3_lo.16b
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tbl v_tmp_hi.16b, {v_gft1_hi.16b}, v_data_3_hi.16b
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eor v_d1_3.16b, v_tmp_lo.16b, v_d1_3.16b
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eor v_d1_3.16b, v_d1_3.16b, v_tmp_hi.16b
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/* dest2 */
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tbl v_tmp_lo.16b, {v_gft2_lo.16b}, v_data_0_lo.16b
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tbl v_tmp_hi.16b, {v_gft2_hi.16b}, v_data_0_hi.16b
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eor v_d2_0.16b, v_tmp_lo.16b, v_d2_0.16b
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eor v_d2_0.16b, v_d2_0.16b, v_tmp_hi.16b
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tbl v_tmp_lo.16b, {v_gft2_lo.16b}, v_data_1_lo.16b
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tbl v_tmp_hi.16b, {v_gft2_hi.16b}, v_data_1_hi.16b
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eor v_d2_1.16b, v_tmp_lo.16b, v_d2_1.16b
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eor v_d2_1.16b, v_d2_1.16b, v_tmp_hi.16b
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tbl v_tmp_lo.16b, {v_gft2_lo.16b}, v_data_2_lo.16b
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tbl v_tmp_hi.16b, {v_gft2_hi.16b}, v_data_2_hi.16b
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eor v_d2_2.16b, v_tmp_lo.16b, v_d2_2.16b
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eor v_d2_2.16b, v_d2_2.16b, v_tmp_hi.16b
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tbl v_tmp_lo.16b, {v_gft2_lo.16b}, v_data_3_lo.16b
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tbl v_tmp_hi.16b, {v_gft2_hi.16b}, v_data_3_hi.16b
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eor v_d2_3.16b, v_tmp_lo.16b, v_d2_3.16b
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eor v_d2_3.16b, v_d2_3.16b, v_tmp_hi.16b
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str q_d1_0, [x_dest1, #16*0]
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str q_d1_1, [x_dest1, #16*1]
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str q_d1_2, [x_dest1, #16*2]
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str q_d1_3, [x_dest1, #16*3]
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add x_dest1, x_dest1, #64
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str q_d2_0, [x_dest2, #16*0]
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str q_d2_1, [x_dest2, #16*1]
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str q_d2_2, [x_dest2, #16*2]
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str q_d2_3, [x_dest2, #16*3]
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add x_dest2, x_dest2, #64
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ldr q_d3_0, [x_dest3, #16*0]
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ldr q_d3_1, [x_dest3, #16*1]
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ldr q_d3_2, [x_dest3, #16*2]
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ldr q_d3_3, [x_dest3, #16*3]
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ldr q_d4_0, [x_dest4, #16*0]
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ldr q_d4_1, [x_dest4, #16*1]
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ldr q_d4_2, [x_dest4, #16*2]
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ldr q_d4_3, [x_dest4, #16*3]
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/* dest3 */
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tbl v_tmp_lo.16b, {v_gft3_lo.16b}, v_data_0_lo.16b
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tbl v_tmp_hi.16b, {v_gft3_hi.16b}, v_data_0_hi.16b
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eor v_d3_0.16b, v_tmp_lo.16b, v_d3_0.16b
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eor v_d3_0.16b, v_d3_0.16b, v_tmp_hi.16b
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tbl v_tmp_lo.16b, {v_gft3_lo.16b}, v_data_1_lo.16b
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tbl v_tmp_hi.16b, {v_gft3_hi.16b}, v_data_1_hi.16b
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eor v_d3_1.16b, v_tmp_lo.16b, v_d3_1.16b
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eor v_d3_1.16b, v_d3_1.16b, v_tmp_hi.16b
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tbl v_tmp_lo.16b, {v_gft3_lo.16b}, v_data_2_lo.16b
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tbl v_tmp_hi.16b, {v_gft3_hi.16b}, v_data_2_hi.16b
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eor v_d3_2.16b, v_tmp_lo.16b, v_d3_2.16b
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eor v_d3_2.16b, v_d3_2.16b, v_tmp_hi.16b
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tbl v_tmp_lo.16b, {v_gft3_lo.16b}, v_data_3_lo.16b
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tbl v_tmp_hi.16b, {v_gft3_hi.16b}, v_data_3_hi.16b
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eor v_d3_3.16b, v_tmp_lo.16b, v_d3_3.16b
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eor v_d3_3.16b, v_d3_3.16b, v_tmp_hi.16b
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/* dest4 */
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tbl v_tmp_lo.16b, {v_gft4_lo.16b}, v_data_0_lo.16b
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tbl v_tmp_hi.16b, {v_gft4_hi.16b}, v_data_0_hi.16b
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eor v_d4_0.16b, v_tmp_lo.16b, v_d4_0.16b
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eor v_d4_0.16b, v_d4_0.16b, v_tmp_hi.16b
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tbl v_tmp_lo.16b, {v_gft4_lo.16b}, v_data_1_lo.16b
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tbl v_tmp_hi.16b, {v_gft4_hi.16b}, v_data_1_hi.16b
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eor v_d4_1.16b, v_tmp_lo.16b, v_d4_1.16b
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eor v_d4_1.16b, v_d4_1.16b, v_tmp_hi.16b
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tbl v_tmp_lo.16b, {v_gft4_lo.16b}, v_data_2_lo.16b
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tbl v_tmp_hi.16b, {v_gft4_hi.16b}, v_data_2_hi.16b
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eor v_d4_2.16b, v_tmp_lo.16b, v_d4_2.16b
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eor v_d4_2.16b, v_d4_2.16b, v_tmp_hi.16b
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tbl v_tmp_lo.16b, {v_gft4_lo.16b}, v_data_3_lo.16b
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tbl v_tmp_hi.16b, {v_gft4_hi.16b}, v_data_3_hi.16b
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eor v_d4_3.16b, v_tmp_lo.16b, v_d4_3.16b
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eor v_d4_3.16b, v_d4_3.16b, v_tmp_hi.16b
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str q_d3_0, [x_dest3, #16*0]
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str q_d3_1, [x_dest3, #16*1]
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str q_d3_2, [x_dest3, #16*2]
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str q_d3_3, [x_dest3, #16*3]
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add x_dest3, x_dest3, #64
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str q_d4_0, [x_dest4, #16*0]
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str q_d4_1, [x_dest4, #16*1]
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str q_d4_2, [x_dest4, #16*2]
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str q_d4_3, [x_dest4, #16*3]
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add x_dest4, x_dest4, #64
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cmp x_src, x_src_end
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bls .Lloop64
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.Lloop64_end:
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/* restore d8 ~ d15 */
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ldp d8, d9, [sp]
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ldp d10, d11, [sp, #16]
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ldp d12, d13, [sp, #32]
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ldp d14, d15, [sp, #48]
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add sp, sp, #64
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add x_src_end, x_src_end, #64
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.Lloop16_init:
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sub x_src_end, x_src_end, #16
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cmp x_src, x_src_end
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bhi .lessthan16_init
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.Lloop16:
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ldr q_data, [x_src]
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ldr q_d1_0, [x_dest1]
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ldr q_d2_0, [x_dest2]
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and v_data_lo.16b, v_data.16b, v_mask0f.16b
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ushr v_data_hi.16b, v_data.16b, #4
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tbl v_tmp_lo.16b, {v_gft1_lo.16b}, v_data_lo.16b
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tbl v_tmp_hi.16b, {v_gft1_hi.16b}, v_data_hi.16b
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eor v_d1_0.16b, v_tmp_lo.16b, v_d1_0.16b
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eor v_d1_0.16b, v_d1_0.16b, v_tmp_hi.16b
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tbl v_tmp_lo.16b, {v_gft2_lo.16b}, v_data_lo.16b
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tbl v_tmp_hi.16b, {v_gft2_hi.16b}, v_data_hi.16b
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eor v_d2_0.16b, v_tmp_lo.16b, v_d2_0.16b
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eor v_d2_0.16b, v_d2_0.16b, v_tmp_hi.16b
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str q_d1_0, [x_dest1]
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str q_d2_0, [x_dest2]
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ldr q_d3_0, [x_dest3]
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ldr q_d4_0, [x_dest4]
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tbl v_tmp_lo.16b, {v_gft3_lo.16b}, v_data_lo.16b
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tbl v_tmp_hi.16b, {v_gft3_hi.16b}, v_data_hi.16b
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eor v_d3_0.16b, v_tmp_lo.16b, v_d3_0.16b
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eor v_d3_0.16b, v_d3_0.16b, v_tmp_hi.16b
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tbl v_tmp_lo.16b, {v_gft4_lo.16b}, v_data_lo.16b
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tbl v_tmp_hi.16b, {v_gft4_hi.16b}, v_data_hi.16b
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eor v_d4_0.16b, v_tmp_lo.16b, v_d4_0.16b
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eor v_d4_0.16b, v_d4_0.16b, v_tmp_hi.16b
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str q_d3_0, [x_dest3]
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str q_d4_0, [x_dest4]
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add x_src, x_src, #16
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add x_dest1, x_dest1, #16
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add x_dest2, x_dest2, #16
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add x_dest3, x_dest3, #16
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add x_dest4, x_dest4, #16
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cmp x_src, x_src_end
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bls .Lloop16
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.lessthan16_init:
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sub x_tmp, x_src, x_src_end
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cmp x_tmp, #16
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beq .return_pass
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.lessthan16:
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mov x_src, x_src_end
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sub x_dest1, x_dest1, x_tmp
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sub x_dest2, x_dest2, x_tmp
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sub x_dest3, x_dest3, x_tmp
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sub x_dest4, x_dest4, x_tmp
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ldr x_const, =const_tbl
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sub x_const, x_const, x_tmp
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ldr q_tmp, [x_const, #16]
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ldr q_data, [x_src]
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ldr q_d1_0, [x_dest1]
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ldr q_d2_0, [x_dest2]
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and v_data_lo.16b, v_data.16b, v_mask0f.16b
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ushr v_data_hi.16b, v_data.16b, #4
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tbl v_tmp_lo.16b, {v_gft1_lo.16b}, v_data_lo.16b
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tbl v_tmp_hi.16b, {v_gft1_hi.16b}, v_data_hi.16b
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eor v_tmp_hi.16b, v_tmp_lo.16b, v_tmp_hi.16b
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and v_tmp_hi.16b, v_tmp_hi.16b, v_tmp.16b
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eor v_d1_0.16b, v_d1_0.16b, v_tmp_hi.16b
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tbl v_tmp_lo.16b, {v_gft2_lo.16b}, v_data_lo.16b
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tbl v_tmp_hi.16b, {v_gft2_hi.16b}, v_data_hi.16b
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eor v_tmp_hi.16b, v_tmp_lo.16b, v_tmp_hi.16b
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and v_tmp_hi.16b, v_tmp_hi.16b, v_tmp.16b
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eor v_d2_0.16b, v_d2_0.16b, v_tmp_hi.16b
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str q_d1_0, [x_dest1]
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str q_d2_0, [x_dest2]
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ldr q_d3_0, [x_dest3]
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ldr q_d4_0, [x_dest4]
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tbl v_tmp_lo.16b, {v_gft3_lo.16b}, v_data_lo.16b
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tbl v_tmp_hi.16b, {v_gft3_hi.16b}, v_data_hi.16b
|
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eor v_tmp_hi.16b, v_tmp_lo.16b, v_tmp_hi.16b
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and v_tmp_hi.16b, v_tmp_hi.16b, v_tmp.16b
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eor v_d3_0.16b, v_d3_0.16b, v_tmp_hi.16b
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tbl v_tmp_lo.16b, {v_gft4_lo.16b}, v_data_lo.16b
|
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tbl v_tmp_hi.16b, {v_gft4_hi.16b}, v_data_hi.16b
|
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eor v_tmp_hi.16b, v_tmp_lo.16b, v_tmp_hi.16b
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and v_tmp_hi.16b, v_tmp_hi.16b, v_tmp.16b
|
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eor v_d4_0.16b, v_d4_0.16b, v_tmp_hi.16b
|
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|
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str q_d3_0, [x_dest3]
|
|
str q_d4_0, [x_dest4]
|
|
|
|
.return_pass:
|
|
mov w_ret, #0
|
|
ret
|
|
|
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.return_fail:
|
|
mov w_ret, #1
|
|
ret
|
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|
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.section .data
|
|
.balign 8
|
|
const_tbl:
|
|
.dword 0x0000000000000000, 0x0000000000000000
|
|
.dword 0xffffffffffffffff, 0xffffffffffffffff
|