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https://github.com/intel/isa-l.git
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239 lines
6.4 KiB
NASM
239 lines
6.4 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2023 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; gf_5vect_mad_avx512_gfni(len, vec, vec_i, mul_array, src, dest);
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;;;
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%include "reg_sizes.asm"
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%include "gf_vect_gfni.inc"
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%if AS_FEATURE_LEVEL >= 10
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%ifidn __OUTPUT_FORMAT__, elf64
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%define arg0 rdi
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%define arg1 rsi
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%define arg2 rdx
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%define arg3 rcx
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%define arg4 r8
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%define arg5 r9
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%define tmp r11
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%define tmp2 r10
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%define func(x) x: endbranch
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%define FUNC_SAVE
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%define FUNC_RESTORE
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%endif
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%ifidn __OUTPUT_FORMAT__, win64
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%define arg0 rcx
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%define arg1 rdx
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%define arg2 r8
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%define arg3 r9
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%define arg4 r12
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%define arg5 r13
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%define tmp r11
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%define tmp2 r10
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%define stack_size 16*10 + 3*8
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%define arg(x) [rsp + stack_size + 8 + 8*x]
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%define func(x) proc_frame x
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%macro FUNC_SAVE 0
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sub rsp, stack_size
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vmovdqa [rsp + 16*0], xmm6
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vmovdqa [rsp + 16*1], xmm7
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vmovdqa [rsp + 16*2], xmm8
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vmovdqa [rsp + 16*3], xmm9
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vmovdqa [rsp + 16*4], xmm10
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vmovdqa [rsp + 16*5], xmm11
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vmovdqa [rsp + 16*6], xmm12
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vmovdqa [rsp + 16*7], xmm13
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vmovdqa [rsp + 16*8], xmm14
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vmovdqa [rsp + 16*9], xmm15
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mov [rsp + 10*16 + 0*8], r12
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mov [rsp + 10*16 + 1*8], r13
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end_prolog
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mov arg4, arg(4)
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mov arg5, arg(5)
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%endmacro
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%macro FUNC_RESTORE 0
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vmovdqa xmm6, [rsp + 16*0]
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vmovdqa xmm7, [rsp + 16*1]
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vmovdqa xmm8, [rsp + 16*2]
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vmovdqa xmm9, [rsp + 16*3]
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vmovdqa xmm10, [rsp + 16*4]
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vmovdqa xmm11, [rsp + 16*5]
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vmovdqa xmm12, [rsp + 16*6]
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vmovdqa xmm13, [rsp + 16*7]
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vmovdqa xmm14, [rsp + 16*8]
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vmovdqa xmm15, [rsp + 16*9]
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mov r12, [rsp + 10*16 + 0*8]
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mov r13, [rsp + 10*16 + 1*8]
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add rsp, stack_size
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%endmacro
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%endif
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%define len arg0
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%define vec arg1
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%define vec_i arg2
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%define mul_array arg3
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%define src arg4
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%define dest1 arg5
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%define pos rax
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%define dest2 tmp2
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%define dest3 mul_array
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%define dest4 vec
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%define dest5 vec_i
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%ifndef EC_ALIGNED_ADDR
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;;; Use Un-aligned load/store
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%define XLDR vmovdqu8
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%define XSTR vmovdqu8
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%else
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;;; Use Non-temporal load/stor
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%ifdef NO_NT_LDST
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%define XLDR vmovdqa64
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%define XSTR vmovdqa64
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%else
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%define XLDR vmovntdqa
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%define XSTR vmovntdq
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%endif
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%endif
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default rel
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[bits 64]
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section .text
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%define x0 zmm0
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%define xd1 zmm1
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%define xd2 zmm2
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%define xd3 zmm3
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%define xd4 zmm4
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%define xd5 zmm5
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%define xgft1 zmm6
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%define xgft2 zmm7
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%define xgft3 zmm8
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%define xgft4 zmm9
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%define xgft5 zmm10
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%define xret1 zmm11
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%define xret2 zmm12
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%define xret3 zmm13
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%define xret4 zmm14
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%define xret5 zmm15
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;;
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;; Encodes 64 bytes of a single source into 5x 64 bytes (parity disks)
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;;
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%macro ENCODE_64B_5 0-1
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%define %%KMASK %1
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%if %0 == 1
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vmovdqu8 x0{%%KMASK}, [src + pos] ;Get next source vector
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vmovdqu8 xd1{%%KMASK}, [dest1 + pos] ;Get next dest vector
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vmovdqu8 xd2{%%KMASK}, [dest2 + pos] ;Get next dest vector
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vmovdqu8 xd3{%%KMASK}, [dest3 + pos] ;Get next dest vector
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vmovdqu8 xd4{%%KMASK}, [dest4 + pos] ;Get next dest vector
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vmovdqu8 xd5{%%KMASK}, [dest5 + pos] ;Get next dest vector
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%else
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XLDR x0, [src + pos] ;Get next source vector
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XLDR xd1, [dest1 + pos] ;Get next dest vector
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XLDR xd2, [dest2 + pos] ;Get next dest vector
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XLDR xd3, [dest3 + pos] ;Get next dest vector
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XLDR xd4, [dest4 + pos] ;Get next dest vector
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XLDR xd5, [dest5 + pos] ;Get next dest vector
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%endif
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GF_MUL_XOR EVEX, x0, xgft1, xret1, xd1, xgft2, xret2, xd2, xgft3, xret3, xd3, \
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xgft4, xret4, xd4, xgft5, xret5, xd5
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%if %0 == 1
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vmovdqu8 [dest1 + pos]{%%KMASK}, xd1
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vmovdqu8 [dest2 + pos]{%%KMASK}, xd2
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vmovdqu8 [dest3 + pos]{%%KMASK}, xd3
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vmovdqu8 [dest4 + pos]{%%KMASK}, xd4
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vmovdqu8 [dest5 + pos]{%%KMASK}, xd5
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%else
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XSTR [dest1 + pos], xd1
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XSTR [dest2 + pos], xd2
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XSTR [dest3 + pos], xd3
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XSTR [dest4 + pos], xd4
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XSTR [dest5 + pos], xd5
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%endif
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%endmacro
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align 16
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mk_global gf_5vect_mad_avx512_gfni, function
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func(gf_5vect_mad_avx512_gfni)
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FUNC_SAVE
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xor pos, pos
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shl vec_i, 3 ;Multiply by 8
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shl vec, 3 ;Multiply by 8
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lea tmp, [mul_array + vec_i]
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vbroadcastf32x2 xgft1, [tmp]
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vbroadcastf32x2 xgft2, [tmp + vec]
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vbroadcastf32x2 xgft3, [tmp + vec*2]
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vbroadcastf32x2 xgft5, [tmp + vec*4]
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add tmp, vec
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vbroadcastf32x2 xgft4, [tmp + vec*2]
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mov dest2, [dest1 + 8]
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mov dest3, [dest1 + 2*8] ; reuse mul_array
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mov dest4, [dest1 + 3*8] ; reuse vec
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mov dest5, [dest1 + 4*8] ; reuse vec_i
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mov dest1, [dest1]
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.loop64:
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ENCODE_64B_5
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add pos, 64 ;Loop on 64 bytes at a time
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sub len, 64
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cmp len, 64
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jge .loop64
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.len_lt_64:
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cmp len, 0
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jle .exit
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xor tmp, tmp
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bts tmp, len
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dec tmp
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kmovq k1, tmp
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ENCODE_64B_5 k1
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.exit:
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vzeroupper
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FUNC_RESTORE
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ret
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endproc_frame
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%endif ; if AS_FEATURE_LEVEL >= 10
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