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cd888f01a4
To support Intel CET, all indirect branch targets must start with ENDBR32/ENDBR64. Here is a patch to define endbranch and add it to function entries in x86 assembly codes which are indirect branch targets as discovered by running testsuite on Intel CET machine and visual inspection. Verified with $ CC="gcc -Wl,-z,cet-report=error -fcf-protection" CXX="g++ -Wl,-z,cet-report=error -fcf-protection" .../configure x86_64-linux $ make -j8 $ make -j8 check with both nasm and yasm on both CET and non-CET machines. Change-Id: I9822578e7294fb5043a64ab7de5c41de81a7d337 Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
586 lines
16 KiB
NASM
586 lines
16 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2020 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Function API:
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; UINT32 crc32_gzip_refl_by16_10(
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; UINT32 init_crc, //initial CRC value, 32 bits
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; const unsigned char *buf, //buffer pointer to calculate CRC on
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; UINT64 len //buffer length in bytes (64-bit data)
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; );
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;
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; Authors:
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; Erdinc Ozturk
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; Vinodh Gopal
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; James Guilford
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;
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; Reference paper titled "Fast CRC Computation for Generic Polynomials Using PCLMULQDQ Instruction"
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; URL: http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
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;
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;
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%include "reg_sizes.asm"
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%ifndef FUNCTION_NAME
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%define FUNCTION_NAME crc32_ieee_by16_10
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%endif
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%if (AS_FEATURE_LEVEL) >= 10
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[bits 64]
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default rel
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section .text
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%ifidn __OUTPUT_FORMAT__, win64
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%xdefine arg1 rcx
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%xdefine arg2 rdx
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%xdefine arg3 r8
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%xdefine arg1_low32 ecx
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%else
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%xdefine arg1 rdi
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%xdefine arg2 rsi
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%xdefine arg3 rdx
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%xdefine arg1_low32 edi
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%endif
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%define TMP 16*0
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%ifidn __OUTPUT_FORMAT__, win64
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%define XMM_SAVE 16*2
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%define VARIABLE_OFFSET 16*12+8
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%else
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%define VARIABLE_OFFSET 16*2+8
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%endif
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align 16
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mk_global FUNCTION_NAME, function
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FUNCTION_NAME:
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endbranch
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not arg1_low32
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sub rsp, VARIABLE_OFFSET
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%ifidn __OUTPUT_FORMAT__, win64
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; push the xmm registers into the stack to maintain
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vmovdqa [rsp + XMM_SAVE + 16*0], xmm6
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vmovdqa [rsp + XMM_SAVE + 16*1], xmm7
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vmovdqa [rsp + XMM_SAVE + 16*2], xmm8
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vmovdqa [rsp + XMM_SAVE + 16*3], xmm9
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vmovdqa [rsp + XMM_SAVE + 16*4], xmm10
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vmovdqa [rsp + XMM_SAVE + 16*5], xmm11
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vmovdqa [rsp + XMM_SAVE + 16*6], xmm12
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vmovdqa [rsp + XMM_SAVE + 16*7], xmm13
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vmovdqa [rsp + XMM_SAVE + 16*8], xmm14
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vmovdqa [rsp + XMM_SAVE + 16*9], xmm15
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%endif
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vbroadcasti32x4 zmm18, [SHUF_MASK]
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cmp arg3, 256
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jl .less_than_256
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; load the initial crc value
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vmovd xmm10, arg1_low32 ; initial crc
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; crc value does not need to be byte-reflected, but it needs to be moved to the high part of the register.
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; because data will be byte-reflected and will align with initial crc at correct place.
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vpslldq xmm10, 12
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; receive the initial 64B data, xor the initial crc value
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vmovdqu8 zmm0, [arg2+16*0]
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vmovdqu8 zmm4, [arg2+16*4]
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vpshufb zmm0, zmm0, zmm18
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vpshufb zmm4, zmm4, zmm18
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vpxorq zmm0, zmm10
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vbroadcasti32x4 zmm10, [rk3] ;xmm10 has rk3 and rk4
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;imm value of pclmulqdq instruction will determine which constant to use
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sub arg3, 256
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cmp arg3, 256
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jl .fold_128_B_loop
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vmovdqu8 zmm7, [arg2+16*8]
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vmovdqu8 zmm8, [arg2+16*12]
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vpshufb zmm7, zmm7, zmm18
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vpshufb zmm8, zmm8, zmm18
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vbroadcasti32x4 zmm16, [rk_1] ;zmm16 has rk-1 and rk-2
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sub arg3, 256
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.fold_256_B_loop:
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add arg2, 256
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vmovdqu8 zmm3, [arg2+16*0]
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vpshufb zmm3, zmm3, zmm18
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vpclmulqdq zmm1, zmm0, zmm16, 0x00
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vpclmulqdq zmm2, zmm0, zmm16, 0x11
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vpxorq zmm0, zmm1, zmm2
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vpxorq zmm0, zmm0, zmm3
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vmovdqu8 zmm9, [arg2+16*4]
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vpshufb zmm9, zmm9, zmm18
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vpclmulqdq zmm5, zmm4, zmm16, 0x00
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vpclmulqdq zmm6, zmm4, zmm16, 0x11
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vpxorq zmm4, zmm5, zmm6
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vpxorq zmm4, zmm4, zmm9
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vmovdqu8 zmm11, [arg2+16*8]
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vpshufb zmm11, zmm11, zmm18
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vpclmulqdq zmm12, zmm7, zmm16, 0x00
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vpclmulqdq zmm13, zmm7, zmm16, 0x11
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vpxorq zmm7, zmm12, zmm13
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vpxorq zmm7, zmm7, zmm11
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vmovdqu8 zmm17, [arg2+16*12]
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vpshufb zmm17, zmm17, zmm18
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vpclmulqdq zmm14, zmm8, zmm16, 0x00
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vpclmulqdq zmm15, zmm8, zmm16, 0x11
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vpxorq zmm8, zmm14, zmm15
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vpxorq zmm8, zmm8, zmm17
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sub arg3, 256
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jge .fold_256_B_loop
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;; Fold 256 into 128
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add arg2, 256
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vpclmulqdq zmm1, zmm0, zmm10, 0x00
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vpclmulqdq zmm2, zmm0, zmm10, 0x11
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vpternlogq zmm7, zmm1, zmm2, 0x96 ; xor ABC
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vpclmulqdq zmm5, zmm4, zmm10, 0x00
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vpclmulqdq zmm6, zmm4, zmm10, 0x11
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vpternlogq zmm8, zmm5, zmm6, 0x96 ; xor ABC
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vmovdqa32 zmm0, zmm7
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vmovdqa32 zmm4, zmm8
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add arg3, 128
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jmp .fold_128_B_register
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; at this section of the code, there is 128*x+y (0<=y<128) bytes of buffer. The fold_128_B_loop
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; loop will fold 128B at a time until we have 128+y Bytes of buffer
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; fold 128B at a time. This section of the code folds 8 xmm registers in parallel
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.fold_128_B_loop:
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add arg2, 128
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vmovdqu8 zmm8, [arg2+16*0]
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vpshufb zmm8, zmm8, zmm18
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vpclmulqdq zmm2, zmm0, zmm10, 0x00
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vpclmulqdq zmm1, zmm0, zmm10, 0x11
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vpxorq zmm0, zmm2, zmm1
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vpxorq zmm0, zmm0, zmm8
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vmovdqu8 zmm9, [arg2+16*4]
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vpshufb zmm9, zmm9, zmm18
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vpclmulqdq zmm5, zmm4, zmm10, 0x00
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vpclmulqdq zmm6, zmm4, zmm10, 0x11
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vpxorq zmm4, zmm5, zmm6
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vpxorq zmm4, zmm4, zmm9
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sub arg3, 128
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jge .fold_128_B_loop
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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add arg2, 128
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; at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
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; the 128B of folded data is in 8 of the xmm registers: xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
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.fold_128_B_register:
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; fold the 8 128b parts into 1 xmm register with different constants
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vmovdqu8 zmm16, [rk9] ; multiply by rk9-rk16
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vmovdqu8 zmm11, [rk17] ; multiply by rk17-rk20, rk1,rk2, 0,0
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vpclmulqdq zmm1, zmm0, zmm16, 0x00
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vpclmulqdq zmm2, zmm0, zmm16, 0x11
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vextracti64x2 xmm7, zmm4, 3 ; save last that has no multiplicand
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vpclmulqdq zmm5, zmm4, zmm11, 0x00
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vpclmulqdq zmm6, zmm4, zmm11, 0x11
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vmovdqa xmm10, [rk1] ; Needed later in reduction loop
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vpternlogq zmm1, zmm2, zmm5, 0x96 ; xor ABC
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vpternlogq zmm1, zmm6, zmm7, 0x96 ; xor ABC
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vshufi64x2 zmm8, zmm1, zmm1, 0x4e ; Swap 1,0,3,2 - 01 00 11 10
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vpxorq ymm8, ymm8, ymm1
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vextracti64x2 xmm5, ymm8, 1
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vpxorq xmm7, xmm5, xmm8
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; instead of 128, we add 128-16 to the loop counter to save 1 instruction from the loop
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; instead of a cmp instruction, we use the negative flag with the jl instruction
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add arg3, 128-16
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jl .final_reduction_for_128
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; now we have 16+y bytes left to reduce. 16 Bytes is in register xmm7 and the rest is in memory
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; we can fold 16 bytes at a time if y>=16
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; continue folding 16B at a time
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.16B_reduction_loop:
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vpclmulqdq xmm8, xmm7, xmm10, 0x11
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vpclmulqdq xmm7, xmm7, xmm10, 0x00
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vpxor xmm7, xmm8
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vmovdqu xmm0, [arg2]
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vpshufb xmm0, xmm0, xmm18
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vpxor xmm7, xmm0
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add arg2, 16
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sub arg3, 16
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; instead of a cmp instruction, we utilize the flags with the jge instruction
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; equivalent of: cmp arg3, 16-16
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; check if there is any more 16B in the buffer to be able to fold
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jge .16B_reduction_loop
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;now we have 16+z bytes left to reduce, where 0<= z < 16.
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;first, we reduce the data in the xmm7 register
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.final_reduction_for_128:
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add arg3, 16
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je .128_done
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; here we are getting data that is less than 16 bytes.
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; since we know that there was data before the pointer, we can offset
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; the input pointer before the actual point, to receive exactly 16 bytes.
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; after that the registers need to be adjusted.
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.get_last_two_xmms:
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vmovdqa xmm2, xmm7
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vmovdqu xmm1, [arg2 - 16 + arg3]
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vpshufb xmm1, xmm18
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; get rid of the extra data that was loaded before
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; load the shift constant
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lea rax, [pshufb_shf_table + 16]
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sub rax, arg3
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vmovdqu xmm0, [rax]
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vpshufb xmm2, xmm0
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vpxor xmm0, [mask1]
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vpshufb xmm7, xmm0
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vpblendvb xmm1, xmm1, xmm2, xmm0
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vpclmulqdq xmm8, xmm7, xmm10, 0x11
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vpclmulqdq xmm7, xmm7, xmm10, 0x00
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vpxor xmm7, xmm8
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vpxor xmm7, xmm1
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.128_done:
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; compute crc of a 128-bit value
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vmovdqa xmm10, [rk5]
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vmovdqa xmm0, xmm7
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;64b fold
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vpclmulqdq xmm7, xmm10, 0x01 ; H*L
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vpslldq xmm0, 8
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vpxor xmm7, xmm0
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;32b fold
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vmovdqa xmm0, xmm7
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vpand xmm0, [mask2]
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vpsrldq xmm7, 12
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vpclmulqdq xmm7, xmm10, 0x10
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vpxor xmm7, xmm0
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;barrett reduction
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.barrett:
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vmovdqa xmm10, [rk7] ; rk7 and rk8 in xmm10
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vmovdqa xmm0, xmm7
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vpclmulqdq xmm7, xmm10, 0x01
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vpslldq xmm7, 4
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vpclmulqdq xmm7, xmm10, 0x11
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vpslldq xmm7, 4
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vpxor xmm7, xmm0
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vpextrd eax, xmm7, 1
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.cleanup:
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not eax
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%ifidn __OUTPUT_FORMAT__, win64
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vmovdqa xmm6, [rsp + XMM_SAVE + 16*0]
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vmovdqa xmm7, [rsp + XMM_SAVE + 16*1]
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vmovdqa xmm8, [rsp + XMM_SAVE + 16*2]
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vmovdqa xmm9, [rsp + XMM_SAVE + 16*3]
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vmovdqa xmm10, [rsp + XMM_SAVE + 16*4]
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vmovdqa xmm11, [rsp + XMM_SAVE + 16*5]
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vmovdqa xmm12, [rsp + XMM_SAVE + 16*6]
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vmovdqa xmm13, [rsp + XMM_SAVE + 16*7]
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vmovdqa xmm14, [rsp + XMM_SAVE + 16*8]
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vmovdqa xmm15, [rsp + XMM_SAVE + 16*9]
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%endif
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add rsp, VARIABLE_OFFSET
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ret
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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align 16
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.less_than_256:
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; check if there is enough buffer to be able to fold 16B at a time
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cmp arg3, 32
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jl .less_than_32
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; if there is, load the constants
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vmovdqa xmm10, [rk1] ; rk1 and rk2 in xmm10
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vmovd xmm0, arg1_low32 ; get the initial crc value
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vpslldq xmm0, 12 ; align it to its correct place
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vmovdqu xmm7, [arg2] ; load the plaintext
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vpshufb xmm7, xmm18 ; byte-reflect the plaintext
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vpxor xmm7, xmm0
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; update the buffer pointer
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add arg2, 16
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; update the counter. subtract 32 instead of 16 to save one instruction from the loop
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sub arg3, 32
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jmp .16B_reduction_loop
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align 16
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.less_than_32:
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; mov initial crc to the return value. this is necessary for zero-length buffers.
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mov eax, arg1_low32
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test arg3, arg3
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je .cleanup
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vmovd xmm0, arg1_low32 ; get the initial crc value
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vpslldq xmm0, 12 ; align it to its correct place
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cmp arg3, 16
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je .exact_16_left
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jl .less_than_16_left
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vmovdqu xmm7, [arg2] ; load the plaintext
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vpshufb xmm7, xmm18
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vpxor xmm7, xmm0 ; xor the initial crc value
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add arg2, 16
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sub arg3, 16
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vmovdqa xmm10, [rk1] ; rk1 and rk2 in xmm10
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jmp .get_last_two_xmms
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align 16
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.less_than_16_left:
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; use stack space to load data less than 16 bytes, zero-out the 16B in memory first.
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vpxor xmm1, xmm1
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mov r11, rsp
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vmovdqa [r11], xmm1
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cmp arg3, 4
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jl .only_less_than_4
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; backup the counter value
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mov r9, arg3
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cmp arg3, 8
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jl .less_than_8_left
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; load 8 Bytes
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mov rax, [arg2]
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mov [r11], rax
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add r11, 8
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sub arg3, 8
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add arg2, 8
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.less_than_8_left:
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cmp arg3, 4
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jl .less_than_4_left
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; load 4 Bytes
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mov eax, [arg2]
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mov [r11], eax
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add r11, 4
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sub arg3, 4
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add arg2, 4
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.less_than_4_left:
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cmp arg3, 2
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jl .less_than_2_left
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; load 2 Bytes
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mov ax, [arg2]
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mov [r11], ax
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add r11, 2
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sub arg3, 2
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add arg2, 2
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.less_than_2_left:
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cmp arg3, 1
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jl .zero_left
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; load 1 Byte
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mov al, [arg2]
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mov [r11], al
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|
.zero_left:
|
|
vmovdqa xmm7, [rsp]
|
|
vpshufb xmm7, xmm18
|
|
vpxor xmm7, xmm0 ; xor the initial crc value
|
|
|
|
lea rax, [pshufb_shf_table + 16]
|
|
sub rax, r9
|
|
vmovdqu xmm0, [rax]
|
|
vpxor xmm0, [mask1]
|
|
|
|
vpshufb xmm7,xmm0
|
|
jmp .128_done
|
|
|
|
align 16
|
|
.exact_16_left:
|
|
vmovdqu xmm7, [arg2]
|
|
vpshufb xmm7, xmm18
|
|
vpxor xmm7, xmm0 ; xor the initial crc value
|
|
jmp .128_done
|
|
|
|
.only_less_than_4:
|
|
cmp arg3, 3
|
|
jl .only_less_than_3
|
|
|
|
; load 3 Bytes
|
|
mov al, [arg2]
|
|
mov [r11], al
|
|
|
|
mov al, [arg2+1]
|
|
mov [r11+1], al
|
|
|
|
mov al, [arg2+2]
|
|
mov [r11+2], al
|
|
|
|
vmovdqa xmm7, [rsp]
|
|
vpshufb xmm7, xmm18
|
|
vpxor xmm7, xmm0 ; xor the initial crc value
|
|
|
|
vpsrldq xmm7, 5
|
|
jmp .barrett
|
|
|
|
.only_less_than_3:
|
|
cmp arg3, 2
|
|
jl .only_less_than_2
|
|
|
|
; load 2 Bytes
|
|
mov al, [arg2]
|
|
mov [r11], al
|
|
|
|
mov al, [arg2+1]
|
|
mov [r11+1], al
|
|
|
|
vmovdqa xmm7, [rsp]
|
|
vpshufb xmm7, xmm18
|
|
vpxor xmm7, xmm0 ; xor the initial crc value
|
|
|
|
vpsrldq xmm7, 6
|
|
jmp .barrett
|
|
|
|
.only_less_than_2:
|
|
; load 1 Byte
|
|
mov al, [arg2]
|
|
mov [r11], al
|
|
|
|
vmovdqa xmm7, [rsp]
|
|
vpshufb xmm7, xmm18
|
|
vpxor xmm7, xmm0 ; xor the initial crc value
|
|
|
|
vpsrldq xmm7, 7
|
|
jmp .barrett
|
|
|
|
section .data
|
|
align 32
|
|
|
|
%ifndef USE_CONSTS
|
|
; precomputed constants
|
|
rk_1: dq 0x1851689900000000
|
|
rk_2: dq 0xa3dc855100000000
|
|
rk1: dq 0xf200aa6600000000
|
|
rk2: dq 0x17d3315d00000000
|
|
rk3: dq 0x022ffca500000000
|
|
rk4: dq 0x9d9ee22f00000000
|
|
rk5: dq 0xf200aa6600000000
|
|
rk6: dq 0x490d678d00000000
|
|
rk7: dq 0x0000000104d101df
|
|
rk8: dq 0x0000000104c11db7
|
|
rk9: dq 0x6ac7e7d700000000
|
|
rk10: dq 0xfcd922af00000000
|
|
rk11: dq 0x34e45a6300000000
|
|
rk12: dq 0x8762c1f600000000
|
|
rk13: dq 0x5395a0ea00000000
|
|
rk14: dq 0x54f2d5c700000000
|
|
rk15: dq 0xd3504ec700000000
|
|
rk16: dq 0x57a8445500000000
|
|
rk17: dq 0xc053585d00000000
|
|
rk18: dq 0x766f1b7800000000
|
|
rk19: dq 0xcd8c54b500000000
|
|
rk20: dq 0xab40b71e00000000
|
|
|
|
rk_1b: dq 0xf200aa6600000000
|
|
rk_2b: dq 0x17d3315d00000000
|
|
dq 0x0000000000000000
|
|
dq 0x0000000000000000
|
|
%else
|
|
INCLUDE_CONSTS
|
|
%endif
|
|
|
|
mask1: dq 0x8080808080808080, 0x8080808080808080
|
|
mask2: dq 0xFFFFFFFFFFFFFFFF, 0x00000000FFFFFFFF
|
|
|
|
SHUF_MASK: dq 0x08090A0B0C0D0E0F, 0x0001020304050607
|
|
|
|
pshufb_shf_table:
|
|
; use these values for shift constants for the pshufb instruction
|
|
; different alignments result in values as shown:
|
|
; dq 0x8887868584838281, 0x008f8e8d8c8b8a89 ; shl 15 (16-1) / shr1
|
|
; dq 0x8988878685848382, 0x01008f8e8d8c8b8a ; shl 14 (16-3) / shr2
|
|
; dq 0x8a89888786858483, 0x0201008f8e8d8c8b ; shl 13 (16-4) / shr3
|
|
; dq 0x8b8a898887868584, 0x030201008f8e8d8c ; shl 12 (16-4) / shr4
|
|
; dq 0x8c8b8a8988878685, 0x04030201008f8e8d ; shl 11 (16-5) / shr5
|
|
; dq 0x8d8c8b8a89888786, 0x0504030201008f8e ; shl 10 (16-6) / shr6
|
|
; dq 0x8e8d8c8b8a898887, 0x060504030201008f ; shl 9 (16-7) / shr7
|
|
; dq 0x8f8e8d8c8b8a8988, 0x0706050403020100 ; shl 8 (16-8) / shr8
|
|
; dq 0x008f8e8d8c8b8a89, 0x0807060504030201 ; shl 7 (16-9) / shr9
|
|
; dq 0x01008f8e8d8c8b8a, 0x0908070605040302 ; shl 6 (16-10) / shr10
|
|
; dq 0x0201008f8e8d8c8b, 0x0a09080706050403 ; shl 5 (16-11) / shr11
|
|
; dq 0x030201008f8e8d8c, 0x0b0a090807060504 ; shl 4 (16-12) / shr12
|
|
; dq 0x04030201008f8e8d, 0x0c0b0a0908070605 ; shl 3 (16-13) / shr13
|
|
; dq 0x0504030201008f8e, 0x0d0c0b0a09080706 ; shl 2 (16-14) / shr14
|
|
; dq 0x060504030201008f, 0x0e0d0c0b0a090807 ; shl 1 (16-15) / shr15
|
|
dq 0x8786858483828100, 0x8f8e8d8c8b8a8988
|
|
dq 0x0706050403020100, 0x000e0d0c0b0a0908
|
|
dq 0x8080808080808080, 0x0f0e0d0c0b0a0908
|
|
dq 0x8080808080808080, 0x8080808080808080
|
|
|
|
%else ; Assembler doesn't understand these opcodes. Add empty symbol for windows.
|
|
%ifidn __OUTPUT_FORMAT__, win64
|
|
global no_ %+ FUNCTION_NAME
|
|
no_ %+ FUNCTION_NAME %+ :
|
|
%endif
|
|
%endif ; (AS_FEATURE_LEVEL) >= 10
|