mirror of
https://github.com/intel/isa-l.git
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8965584ae3
Move current level 2 compression to be level 3 and create a level 2 compression which is the same algorithm as level 1 but with a larger hashtable. Change-Id: I398a6017c2ff218dded24e229fb51c23ea69f314 Signed-off-by: Roy Oursler <roy.j.oursler@intel.com>
162 lines
7.2 KiB
NASM
162 lines
7.2 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2016 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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default rel
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[bits 64]
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%include "reg_sizes.asm"
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extern isal_deflate_body_base
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extern isal_deflate_body_01
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extern isal_deflate_body_02
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extern isal_deflate_body_04
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extern isal_deflate_finish_base
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extern isal_deflate_finish_01
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extern isal_deflate_icf_body_hash8k_base
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extern isal_deflate_icf_body_hash8k_01
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extern isal_deflate_icf_body_hash8k_02
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extern isal_deflate_icf_body_hash8k_04
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extern isal_deflate_icf_finish_hash8k_base
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extern isal_deflate_icf_finish_hash8k_01
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extern isal_deflate_icf_body_hash_hist_base
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extern isal_deflate_icf_body_hash_hist_01
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extern isal_deflate_icf_body_hash_hist_02
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extern isal_deflate_icf_body_hash_hist_04
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extern isal_deflate_icf_finish_hash_hist_base
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extern isal_deflate_icf_finish_hash_hist_01
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extern isal_deflate_icf_finish_hash_map_base
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extern isal_update_histogram_base
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extern isal_update_histogram_01
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extern isal_update_histogram_04
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extern gen_icf_map_h1_base
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extern encode_deflate_icf_base
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extern encode_deflate_icf_04
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extern set_long_icf_fg_base
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%ifdef HAVE_AS_KNOWS_AVX512
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extern encode_deflate_icf_06
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extern set_long_icf_fg_06
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extern gen_icf_map_lh1_06
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%endif
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extern crc32_gzip_base
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extern crc32_gzip_01
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extern adler32_base
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extern adler32_avx2_4
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extern adler32_sse
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extern isal_deflate_hash_base
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extern isal_deflate_hash_crc_01
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extern isal_deflate_hash_mad_base
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extern isal_deflate_icf_body_base
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extern isal_deflate_icf_body_06
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section .text
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%include "multibinary.asm"
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mbin_interface isal_deflate_body
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mbin_dispatch_init5 isal_deflate_body, isal_deflate_body_base, isal_deflate_body_01, isal_deflate_body_02, isal_deflate_body_04
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mbin_interface isal_deflate_finish
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mbin_dispatch_init5 isal_deflate_finish, isal_deflate_finish_base, isal_deflate_finish_01, isal_deflate_finish_01, isal_deflate_finish_01
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mbin_interface isal_deflate_icf_body_lvl1
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mbin_dispatch_init5 isal_deflate_icf_body_lvl1, isal_deflate_icf_body_hash8k_base, isal_deflate_icf_body_hash8k_01, isal_deflate_icf_body_hash8k_02, isal_deflate_icf_body_hash8k_04
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mbin_interface isal_deflate_icf_body_lvl2
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mbin_dispatch_init5 isal_deflate_icf_body_lvl2, isal_deflate_icf_body_hash_hist_base, isal_deflate_icf_body_hash_hist_01, isal_deflate_icf_body_hash_hist_02, isal_deflate_icf_body_hash_hist_04
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mbin_interface isal_deflate_icf_finish_lvl1
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mbin_dispatch_init5 isal_deflate_icf_finish_lvl1, isal_deflate_icf_finish_hash8k_base, isal_deflate_icf_finish_hash8k_01, isal_deflate_icf_finish_hash8k_01, isal_deflate_icf_finish_hash8k_01
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mbin_interface isal_deflate_icf_finish_lvl2
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mbin_dispatch_init5 isal_deflate_icf_finish_lvl2, isal_deflate_icf_finish_hash_hist_base, isal_deflate_icf_finish_hash_hist_01, isal_deflate_icf_finish_hash_hist_01, isal_deflate_icf_finish_hash_hist_01
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mbin_interface isal_deflate_icf_finish_lvl3
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mbin_dispatch_init5 isal_deflate_icf_finish_lvl3, isal_deflate_icf_finish_hash_map_base, isal_deflate_icf_finish_hash_map_base, isal_deflate_icf_finish_hash_map_base, isal_deflate_icf_finish_hash_map_base
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mbin_interface isal_update_histogram
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mbin_dispatch_init5 isal_update_histogram, isal_update_histogram_base, isal_update_histogram_01, isal_update_histogram_01, isal_update_histogram_04
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%ifdef HAVE_AS_KNOWS_AVX512
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mbin_interface encode_deflate_icf
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mbin_dispatch_init6 encode_deflate_icf, encode_deflate_icf_base, encode_deflate_icf_base, encode_deflate_icf_base, encode_deflate_icf_04, encode_deflate_icf_06
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mbin_interface set_long_icf_fg
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mbin_dispatch_init6 set_long_icf_fg, set_long_icf_fg_base, set_long_icf_fg_base, set_long_icf_fg_base, set_long_icf_fg_base, set_long_icf_fg_06
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mbin_interface gen_icf_map_lh1
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mbin_dispatch_init6 gen_icf_map_lh1, gen_icf_map_h1_base, gen_icf_map_h1_base, gen_icf_map_h1_base, gen_icf_map_h1_base, gen_icf_map_lh1_06
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%else
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mbin_interface encode_deflate_icf
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mbin_dispatch_init5 encode_deflate_icf, encode_deflate_icf_base, encode_deflate_icf_base, encode_deflate_icf_base, encode_deflate_icf_04
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mbin_interface set_long_icf_fg
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mbin_dispatch_init5 set_long_icf_fg, set_long_icf_fg_base, set_long_icf_fg_base, set_long_icf_fg_base, set_long_icf_fg_base
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mbin_interface gen_icf_map_lh1
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mbin_dispatch_init5 gen_icf_map_lh1, gen_icf_map_h1_base, gen_icf_map_h1_base, gen_icf_map_h1_base, gen_icf_map_h1_base
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%endif
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mbin_interface crc32_gzip
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mbin_dispatch_init_clmul crc32_gzip, crc32_gzip_base, crc32_gzip_01
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mbin_interface isal_adler32
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mbin_dispatch_init5 isal_adler32, adler32_base, adler32_sse, adler32_sse, adler32_avx2_4
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mbin_interface isal_deflate_hash_lvl0
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mbin_dispatch_init5 isal_deflate_hash_lvl0, isal_deflate_hash_base, isal_deflate_hash_crc_01, isal_deflate_hash_crc_01, isal_deflate_hash_crc_01
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mbin_interface isal_deflate_hash_lvl1
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mbin_dispatch_init5 isal_deflate_hash_lvl1, isal_deflate_hash_base, isal_deflate_hash_crc_01, isal_deflate_hash_crc_01, isal_deflate_hash_crc_01
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mbin_interface isal_deflate_hash_lvl2
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mbin_dispatch_init5 isal_deflate_hash_lvl2, isal_deflate_hash_base, isal_deflate_hash_crc_01, isal_deflate_hash_crc_01, isal_deflate_hash_crc_01
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mbin_interface isal_deflate_hash_lvl3
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mbin_dispatch_init5 isal_deflate_hash_lvl3, isal_deflate_hash_base, isal_deflate_hash_base, isal_deflate_hash_base, isal_deflate_hash_mad_base
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%ifdef HAVE_AS_KNOWS_AVX512
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mbin_interface isal_deflate_icf_body
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mbin_dispatch_init6 isal_deflate_icf_body, isal_deflate_icf_body_base, isal_deflate_icf_body_base, isal_deflate_icf_body_base, isal_deflate_icf_body_base, isal_deflate_icf_body_06
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%else
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mbin_interface isal_deflate_icf_body
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mbin_dispatch_init5 isal_deflate_icf_body, isal_deflate_icf_body_base, isal_deflate_icf_body_base, isal_deflate_icf_body_base, isal_deflate_icf_body_base
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%endif
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