mirror of
https://github.com/intel/isa-l.git
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1187583a97
- It should be fine to enable pmull always on Apple Silicon - macOS 12+ is required for PMULL instruction. - Changed the conditional macro to __APPLE__ - Rewritten dispatcher using sysctlbyname - Use __USER_LABEL_PREFIX__ - Use __TEXT,__const as readonly section - use ASM_DEF_RODATA macro - fix func decl Change-Id: I800593f21085d8187b480c8bb3ab2bd70c4a6974 Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>
147 lines
4.1 KiB
C
147 lines
4.1 KiB
C
########################################################################
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# Copyright(c) 2019 Arm Corporation All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in
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# the documentation and/or other materials provided with the
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# distribution.
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# * Neither the name of Arm Corporation nor the names of its
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# contributors may be used to endorse or promote products derived
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# from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#########################################################################
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#include "crc_common_pmull.h"
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.macro crc32_norm_func name:req
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.arch armv8-a+crypto
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.text
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.align 3
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.global cdecl(\name)
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#ifndef __APPLE__
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.type \name, %function
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#endif
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/* uint32_t crc32_norm_func(uint32_t seed, uint8_t * buf, uint64_t len) */
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cdecl(\name\()):
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mvn w_seed, w_seed
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mov x_counter, 0
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cmp x_len, (FOLD_SIZE - 1)
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bhi .crc_clmul_pre
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.crc_tab_pre:
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cmp x_len, x_counter
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bls .done
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#ifndef __APPLE__
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adrp x_tmp, .lanchor_crc_tab
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add x_buf_iter, x_buf, x_counter
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add x_buf, x_buf, x_len
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add x_crc_tab_addr, x_tmp, :lo12:.lanchor_crc_tab
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#else
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adrp x_tmp, .lanchor_crc_tab@PAGE
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add x_buf_iter, x_buf, x_counter
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add x_buf, x_buf, x_len
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add x_crc_tab_addr, x_tmp, .lanchor_crc_tab@PAGEOFF
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#endif
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.align 3
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.loop_crc_tab:
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ldrb w_tmp, [x_buf_iter], 1
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cmp x_buf, x_buf_iter
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eor w_tmp, w_tmp, w_seed, lsr 24
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ldr w_tmp, [x_crc_tab_addr, w_tmp, uxtw 2]
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eor w_seed, w_tmp, w_seed, lsl 8
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bhi .loop_crc_tab
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.done:
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mvn w_crc_ret, w_seed
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ret
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.align 2
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.crc_clmul_pre:
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lsl x_seed, x_seed, 32
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movi v_x0.2s, 0
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fmov v_x0.d[1], x_seed // save crc to v_x0
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crc_norm_load_first_block
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bls .clmul_loop_end
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crc32_load_p4
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// 1024bit --> 512bit loop
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// merge x0, x1, x2, x3, y0, y1, y2, y3 => x0, x1, x2, x3 (uint64x2_t)
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crc_norm_loop
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.clmul_loop_end:
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// folding 512bit --> 128bit
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crc32_fold_512b_to_128b
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// folding 128bit --> 64bit
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mov x_tmp, p0_high_b0
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movk x_tmp, p0_high_b1, lsl 16
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fmov d_p0_high, x_tmp
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mov x_tmp2, p0_low_b0
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movk x_tmp2, p0_low_b1, lsl 16
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fmov d_p0_high2, x_tmp2
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mov d_tmp_high, v_x3.d[0]
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ext v_tmp_high.16b, v_tmp_high.16b, v_tmp_high.16b, #12
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pmull2 v_x3.1q, v_x3.2d, v_p0.2d
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eor v_tmp_high.16b, v_tmp_high.16b, v_x3.16b
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pmull2 v_x3.1q, v_tmp_high.2d, v_p02.2d
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// barrett reduction
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mov x_tmp2, br_high_b0
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movk x_tmp2, br_high_b1, lsl 16
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movk x_tmp2, br_high_b2, lsl 32
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fmov d_br_high, x_tmp2
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mov x_tmp, br_low_b0
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movk x_tmp, br_low_b1, lsl 16
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movk x_tmp, br_low_b2, lsl 32
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fmov d_br_low, x_tmp
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eor v_tmp_high.16b, v_tmp_high.16b, v_x3.16b
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mov s_x3, v_tmp_high.s[1]
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pmull v_x3.1q, v_x3.1d, v_br_low.1d
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mov s_x3, v_x3.s[1]
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pmull v_x3.1q, v_x3.1d, v_br_high.1d
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eor v_tmp_high.8b, v_tmp_high.8b, v_x3.8b
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umov w_seed, v_tmp_high.s[0]
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b .crc_tab_pre
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#ifndef __APPLE__
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.size \name, .-\name
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.section .rodata.cst16,"aM",@progbits,16
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#else
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.section __TEXT,__const
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#endif
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.align 4
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.shuffle_data:
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.byte 15, 14, 13, 12, 11, 10, 9
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.byte 8, 7, 6, 5, 4, 3, 2, 1, 0
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.endm
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