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cd888f01a4
To support Intel CET, all indirect branch targets must start with ENDBR32/ENDBR64. Here is a patch to define endbranch and add it to function entries in x86 assembly codes which are indirect branch targets as discovered by running testsuite on Intel CET machine and visual inspection. Verified with $ CC="gcc -Wl,-z,cet-report=error -fcf-protection" CXX="g++ -Wl,-z,cet-report=error -fcf-protection" .../configure x86_64-linux $ make -j8 $ make -j8 check with both nasm and yasm on both CET and non-CET machines. Change-Id: I9822578e7294fb5043a64ab7de5c41de81a7d337 Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
237 lines
6.1 KiB
NASM
237 lines
6.1 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; gf_2vect_mad_avx(len, vec, vec_i, mul_array, src, dest);
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;;;
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%include "reg_sizes.asm"
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%define PS 8
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%ifidn __OUTPUT_FORMAT__, win64
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%define arg0 rcx
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%define arg0.w ecx
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%define arg1 rdx
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%define arg2 r8
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%define arg3 r9
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%define arg4 r12
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%define arg5 r15
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%define tmp r11
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%define tmp2 r10
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%define return rax
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%define return.w eax
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%define stack_size 16*9 + 3*8
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%define arg(x) [rsp + stack_size + PS + PS*x]
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%define func(x) proc_frame x
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%macro FUNC_SAVE 0
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sub rsp, stack_size
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movdqa [rsp+16*0],xmm6
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movdqa [rsp+16*1],xmm7
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movdqa [rsp+16*2],xmm8
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movdqa [rsp+16*3],xmm9
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movdqa [rsp+16*4],xmm10
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movdqa [rsp+16*5],xmm11
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movdqa [rsp+16*6],xmm12
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movdqa [rsp+16*7],xmm13
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movdqa [rsp+16*8],xmm14
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save_reg r12, 9*16 + 0*8
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save_reg r15, 9*16 + 1*8
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end_prolog
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mov arg4, arg(4)
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mov arg5, arg(5)
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%endmacro
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%macro FUNC_RESTORE 0
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movdqa xmm6, [rsp+16*0]
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movdqa xmm7, [rsp+16*1]
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movdqa xmm8, [rsp+16*2]
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movdqa xmm9, [rsp+16*3]
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movdqa xmm10, [rsp+16*4]
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movdqa xmm11, [rsp+16*5]
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movdqa xmm12, [rsp+16*6]
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movdqa xmm13, [rsp+16*7]
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movdqa xmm14, [rsp+16*8]
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mov r12, [rsp + 9*16 + 0*8]
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mov r15, [rsp + 9*16 + 1*8]
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add rsp, stack_size
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%endmacro
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%elifidn __OUTPUT_FORMAT__, elf64
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%define arg0 rdi
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%define arg0.w edi
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%define arg1 rsi
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%define arg2 rdx
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%define arg3 rcx
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%define arg4 r8
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%define arg5 r9
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%define tmp r11
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%define tmp2 r10
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%define return rax
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%define return.w eax
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%define func(x) x: endbranch
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%define FUNC_SAVE
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%define FUNC_RESTORE
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%endif
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;;; gf_2vect_mad_avx(len, vec, vec_i, mul_array, src, dest)
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%define len arg0
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%define len.w arg0.w
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%define vec arg1
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%define vec_i arg2
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%define mul_array arg3
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%define src arg4
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%define dest1 arg5
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%define pos return
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%define pos.w return.w
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%define dest2 tmp2
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%ifndef EC_ALIGNED_ADDR
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;;; Use Un-aligned load/store
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%define XLDR vmovdqu
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%define XSTR vmovdqu
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%else
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;;; Use Non-temporal load/stor
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%ifdef NO_NT_LDST
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%define XLDR vmovdqa
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%define XSTR vmovdqa
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%else
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%define XLDR vmovntdqa
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%define XSTR vmovntdq
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%endif
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%endif
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default rel
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[bits 64]
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section .text
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%define xmask0f xmm14
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%define xgft1_lo xmm13
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%define xgft1_hi xmm12
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%define xgft2_lo xmm11
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%define xgft2_hi xmm10
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%define x0 xmm0
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%define xtmpa xmm1
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%define xtmph1 xmm2
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%define xtmpl1 xmm3
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%define xtmph2 xmm4
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%define xtmpl2 xmm5
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%define xd1 xmm6
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%define xd2 xmm7
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%define xtmpd1 xmm8
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%define xtmpd2 xmm9
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align 16
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mk_global gf_2vect_mad_avx, function
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func(gf_2vect_mad_avx)
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FUNC_SAVE
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sub len, 16
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jl .return_fail
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xor pos, pos
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vmovdqa xmask0f, [mask0f] ;Load mask of lower nibble in each byte
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sal vec_i, 5 ;Multiply by 32
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sal vec, 5
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lea tmp, [mul_array + vec_i]
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vmovdqu xgft1_lo, [tmp] ;Load array Ax{00}, Ax{01}, Ax{02}, ...
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vmovdqu xgft1_hi, [tmp+16] ; " Ax{00}, Ax{10}, Ax{20}, ... , Ax{f0}
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vmovdqu xgft2_lo, [tmp+vec] ;Load array Bx{00}, Bx{01}, Bx{02}, ...
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vmovdqu xgft2_hi, [tmp+vec+16] ; " Bx{00}, Bx{10}, Bx{20}, ... , Bx{f0}
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mov dest2, [dest1+PS]
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mov dest1, [dest1]
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XLDR xtmpd1, [dest1+len] ;backup the last 16 bytes in dest
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XLDR xtmpd2, [dest2+len] ;backup the last 16 bytes in dest
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.loop16:
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XLDR xd1, [dest1+pos] ;Get next dest vector
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XLDR xd2, [dest2+pos] ;Get next dest vector
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.loop16_overlap:
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XLDR x0, [src+pos] ;Get next source vector
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vpand xtmpa, x0, xmask0f ;Mask low src nibble in bits 4-0
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vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
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vpand x0, x0, xmask0f ;Mask high src nibble in bits 4-0
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vpshufb xtmph1, xgft1_hi, x0 ;Lookup mul table of high nibble
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vpshufb xtmpl1, xgft1_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xtmph1, xtmph1, xtmpl1 ;GF add high and low partials
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vpxor xd1, xd1, xtmph1 ;xd1 += partial
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vpshufb xtmph2, xgft2_hi, x0 ;Lookup mul table of high nibble
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vpshufb xtmpl2, xgft2_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xtmph2, xtmph2, xtmpl2 ;GF add high and low partials
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vpxor xd2, xd2, xtmph2 ;xd2 += partial
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XSTR [dest1+pos], xd1
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XSTR [dest2+pos], xd2
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add pos, 16 ;Loop on 16 bytes at a time
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cmp pos, len
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jle .loop16
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lea tmp, [len + 16]
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cmp pos, tmp
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je .return_pass
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;; Tail len
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mov pos, len ;Overlapped offset length-16
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vmovdqa xd1, xtmpd1 ;Restore xd1
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vmovdqa xd2, xtmpd2 ;Restore xd2
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jmp .loop16_overlap ;Do one more overlap pass
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.return_pass:
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mov return, 0
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FUNC_RESTORE
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ret
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.return_fail:
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mov return, 1
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FUNC_RESTORE
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ret
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endproc_frame
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section .data
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align 16
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mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
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;;; func core, ver, snum
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slversion gf_2vect_mad_avx, 02, 01, 0204
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