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660f49b02d
Include fast DEFLATE compatable compression functions. Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
195 lines
5.1 KiB
NASM
195 lines
5.1 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2016 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%include "options.asm"
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%include "reg_sizes.asm"
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; Functional versions of CRC macros
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%include "igzip_buffer_utils_04.asm"
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extern fold_4
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%define crc_0 xmm0 ; in/out: crc state
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%define crc_1 xmm1 ; in/out: crc state
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%define crc_2 xmm2 ; in/out: crc state
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%define crc_3 xmm3 ; in/out: crc state
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%define crc_fold xmm4 ; in: (loaded from fold_4)
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%define crc_tmp0 xmm5 ; tmp
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%define crc_tmp1 xmm6 ; tmp
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%define crc_tmp2 xmm7 ; tmp
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%define crc_tmp3 xmm8 ; tmp
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%define crc_tmp4 xmm9 ; tmp
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%define tmp4 rax
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; copy x bytes (rounded up to 16 bytes) from src to dst with crc
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; src & dst are unaligned
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; void copy_in_crc(uint8_t *dst, uint8_t *src, uint32_t size, uint32_t *crc)
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; arg 1: rcx: pointer to dst
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; arg 2: rdx: pointer to src
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; arg 3: r8: size (in bytes)
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; arg 4: r9: pointer to CRC
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;; %if 0
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global copy_in_crc_04
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copy_in_crc_04:
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%ifidn __OUTPUT_FORMAT__, elf64
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mov r9, rcx
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mov r8, rdx
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mov rdx, rsi
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mov rcx, rdi
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%endif
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; Save xmm registers that need to be preserved.
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sub rsp, 8 + 4*16
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vmovdqa [rsp+0*16], xmm6
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vmovdqa [rsp+1*16], xmm7
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vmovdqa [rsp+2*16], xmm8
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vmovdqa [rsp+3*16], xmm9
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vmovdqa crc_0, [r9 + 0*16]
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vmovdqa crc_1, [r9 + 1*16]
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vmovdqa crc_2, [r9 + 2*16]
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vmovdqa crc_3, [r9 + 3*16]
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vmovdqa crc_fold, [fold_4 WRT_OPT]
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COPY_IN_CRC rcx, rdx, r8, tmp4, crc_0, crc_1, crc_2, crc_3, \
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crc_fold, \
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crc_tmp0, crc_tmp1, crc_tmp2, crc_tmp3, crc_tmp4
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vmovdqa [r9 + 0*16], crc_0
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vmovdqa [r9 + 1*16], crc_1
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vmovdqa [r9 + 2*16], crc_2
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vmovdqa [r9 + 3*16], crc_3
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vmovdqa xmm9, [rsp+3*16]
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vmovdqa xmm8, [rsp+2*16]
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vmovdqa xmm7, [rsp+1*16]
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vmovdqa xmm6, [rsp+0*16]
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add rsp, 8 + 4*16
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ret
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; Convert 512-bit CRC data to real 32-bit value
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; uint32_t crc_512to32(uint32_t *crc)
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; arg 1: rcx: pointer to CRC
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; returns: eax: 32 bit crc
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global crc_512to32_04
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crc_512to32_04:
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%ifidn __OUTPUT_FORMAT__, elf64
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mov rcx, rdi
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%endif
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vmovdqa crc_0, [rcx + 0*16]
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vmovdqa crc_1, [rcx + 1*16]
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vmovdqa crc_2, [rcx + 2*16]
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vmovdqa crc_3, [rcx + 3*16]
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vmovdqa crc_fold, [rk1 WRT_OPT] ;k1
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; fold the 4 xmm registers to 1 xmm register with different constants
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vmovdqa crc_tmp0, crc_0
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vpclmulqdq crc_0, crc_fold, 0x1
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vpclmulqdq crc_tmp0, crc_fold, 0x10
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vpxor crc_1, crc_tmp0
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vpxor crc_1, crc_0
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vmovdqa crc_tmp0, crc_1
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vpclmulqdq crc_1, crc_fold, 0x1
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vpclmulqdq crc_tmp0, crc_fold, 0x10
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vpxor crc_2, crc_tmp0
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vpxor crc_2, crc_1
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vmovdqa crc_tmp0, crc_2
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vpclmulqdq crc_2, crc_fold, 0x1
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vpclmulqdq crc_tmp0, crc_fold, 0x10
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vpxor crc_3, crc_tmp0
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vpxor crc_3, crc_2
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vmovdqa crc_fold, [rk5 WRT_OPT]
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vmovdqa crc_0, crc_3
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vpclmulqdq crc_3, crc_fold, 0
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vpsrldq crc_0, 8
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vpxor crc_3, crc_0
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vmovdqa crc_0, crc_3
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vpslldq crc_3, 4
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vpclmulqdq crc_3, crc_fold, 0x10
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vpxor crc_3, crc_0
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vpand crc_3, [mask2 WRT_OPT]
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vmovdqa crc_1, crc_3
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vmovdqa crc_2, crc_3
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vmovdqa crc_fold, [rk7 WRT_OPT]
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vpclmulqdq crc_3, crc_fold, 0
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vpxor crc_3, crc_2
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vpand crc_3, [mask WRT_OPT]
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vmovdqa crc_2, crc_3
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vpclmulqdq crc_3, crc_fold, 0x10
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vpxor crc_3, crc_2
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vpxor crc_3, crc_1
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vpextrd eax, crc_3, 2
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not eax
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ret
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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section .data
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align 16
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rk1: dq 0x00000000ccaa009e
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rk2: dq 0x00000001751997d0
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rk5: dq 0x00000000ccaa009e
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rk6: dq 0x0000000163cd6124
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rk7: dq 0x00000001f7011640
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rk8: dq 0x00000001db710640
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mask: dq 0xFFFFFFFFFFFFFFFF, 0x0000000000000000
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mask2: dq 0xFFFFFFFF00000000, 0xFFFFFFFFFFFFFFFF
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