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4815174a68
Arrange the two xor instructions according to the specified paradigm, then the two xor instructions can be fused to execute which can save one issue slot and one execution latency. Change-Id: Ic64bcfe569b2468e4dc9c13d073d367cc81fd937 Signed-off-by: liuqinfei <lucas.liuqinfei@huawei.com>
312 lines
8.4 KiB
C
312 lines
8.4 KiB
C
########################################################################
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# Copyright (c) 2019 Microsoft Corporation.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in
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# the documentation and/or other materials provided with the
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# distribution.
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# * Neither the name of Microsoft Corporation nor the names of its
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# contributors may be used to endorse or promote products derived
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# from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#########################################################################
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#include "../include/aarch64_label.h"
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// parameters
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#define w_seed w0
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#define x_seed x0
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#define x_buf x1
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#define w_len w2
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#define x_len x2
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// return
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#define w_crc_ret w0
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#define x_crc_ret x0
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// constant
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#define FOLD_SIZE 64
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// global variables
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#define x_buf_end x3
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#define w_counter w4
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#define x_counter x4
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#define x_buf_iter x5
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#define x_crc_tab_addr x6
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#define x_tmp2 x6
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#define w_tmp w7
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#define x_tmp x7
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#define v_x0 v0
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#define d_x0 d0
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#define s_x0 s0
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#define q_x1 q1
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#define v_x1 v1
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#define q_x2 q2
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#define v_x2 v2
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#define q_x3 q3
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#define v_x3 v3
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#define d_x3 d3
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#define s_x3 s3
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#define q_y0 q4
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#define v_y0 v4
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#define v_tmp_high v4
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#define d_tmp_high d4
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#define q_y1 q5
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#define v_y1 v5
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#define v_tmp_low v5
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#define q_y2 q6
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#define v_y2 v6
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#define q_y3 q7
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#define v_y3 v7
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#define q_x0_tmp q30
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#define v_x0_tmp v30
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#define d_p4_high v30.d[1]
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#define d_p4_low d30
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#define v_p4 v30
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#define d_p1_high v30.d[1]
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#define d_p1_low d30
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#define v_p1 v30
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#define d_p0_high v30.d[1]
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#define d_p0_low d30
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#define v_p0 v30
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#define d_br_low d30
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#define d_br_low2 v30.d[1]
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#define v_br_low v30
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#define q_shuffle q31
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#define v_shuffle v31
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#define d_br_high d31
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#define d_br_high2 v31.d[1]
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#define v_br_high v31
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#define d_p0_low2 d31
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#define d_p0_high2 v31.d[1]
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#define v_p02 v31
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#define v_x0_high v16
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#define v_x1_high v17
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#define v_x2_high v18
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#define v_x3_high v19
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.macro crc_refl_load_first_block
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ldr q_x0_tmp, [x_buf]
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ldr q_x1, [x_buf, 16]
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ldr q_x2, [x_buf, 32]
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ldr q_x3, [x_buf, 48]
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and x_counter, x_len, -64
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sub x_tmp, x_counter, #64
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cmp x_tmp, 63
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add x_buf_iter, x_buf, 64
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eor v_x0.16b, v_x0.16b, v_x0_tmp.16b
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.endm
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.macro crc_norm_load_first_block
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#ifndef __APPLE__
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adrp x_tmp, .shuffle_data
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ldr q_shuffle, [x_tmp, #:lo12:.shuffle_data]
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#else
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adrp x_tmp, .shuffle_data@PAGE
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ldr q_shuffle, [x_tmp, #.shuffle_data@PAGEOFF]
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#endif
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ldr q_x0_tmp, [x_buf]
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ldr q_x1, [x_buf, 16]
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ldr q_x2, [x_buf, 32]
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ldr q_x3, [x_buf, 48]
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and x_counter, x_len, -64
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sub x_tmp, x_counter, #64
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cmp x_tmp, 63
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add x_buf_iter, x_buf, 64
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tbl v_x0_tmp.16b, {v_x0_tmp.16b}, v_shuffle.16b
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tbl v_x1.16b, {v_x1.16b}, v_shuffle.16b
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tbl v_x2.16b, {v_x2.16b}, v_shuffle.16b
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tbl v_x3.16b, {v_x3.16b}, v_shuffle.16b
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eor v_x0.16b, v_x0.16b, v_x0_tmp.16b
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.endm
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.macro crc32_load_p4
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add x_buf_end, x_buf_iter, x_tmp
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mov x_tmp, p4_low_b0
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movk x_tmp, p4_low_b1, lsl 16
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fmov d_p4_low, x_tmp
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mov x_tmp2, p4_high_b0
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movk x_tmp2, p4_high_b1, lsl 16
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fmov d_p4_high, x_tmp2
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.endm
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.macro crc64_load_p4
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add x_buf_end, x_buf_iter, x_tmp
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mov x_tmp, p4_low_b0
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movk x_tmp, p4_low_b1, lsl 16
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movk x_tmp, p4_low_b2, lsl 32
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movk x_tmp, p4_low_b3, lsl 48
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fmov d_p4_low, x_tmp
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mov x_tmp2, p4_high_b0
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movk x_tmp2, p4_high_b1, lsl 16
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movk x_tmp2, p4_high_b2, lsl 32
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movk x_tmp2, p4_high_b3, lsl 48
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fmov d_p4_high, x_tmp2
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.endm
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.macro crc_refl_loop
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.align 3
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.clmul_loop:
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// interleave ldr and pmull(2) for arch which can only issue quadword load every
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// other cycle (i.e. A55)
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ldr q_y0, [x_buf_iter]
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pmull2 v_x0_high.1q, v_x0.2d, v_p4.2d
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ldr q_y1, [x_buf_iter, 16]
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pmull2 v_x1_high.1q, v_x1.2d, v_p4.2d
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ldr q_y2, [x_buf_iter, 32]
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pmull2 v_x2_high.1q, v_x2.2d, v_p4.2d
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ldr q_y3, [x_buf_iter, 48]
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pmull2 v_x3_high.1q, v_x3.2d, v_p4.2d
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pmull v_x0.1q, v_x0.1d, v_p4.1d
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add x_buf_iter, x_buf_iter, 64
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pmull v_x1.1q, v_x1.1d, v_p4.1d
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cmp x_buf_iter, x_buf_end
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pmull v_x2.1q, v_x2.1d, v_p4.1d
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pmull v_x3.1q, v_x3.1d, v_p4.1d
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eor v_x0.16b, v_x0_high.16b, v_x0.16b
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eor v_x0.16b, v_x0.16b, v_y0.16b
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eor v_x1.16b, v_x1_high.16b, v_x1.16b
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eor v_x1.16b, v_x1.16b, v_y1.16b
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eor v_x2.16b, v_x2_high.16b, v_x2.16b
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eor v_x2.16b, v_x2.16b, v_y2.16b
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eor v_x3.16b, v_x3_high.16b, v_x3.16b
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eor v_x3.16b, v_x3.16b, v_y3.16b
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bne .clmul_loop
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.endm
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.macro crc_norm_loop
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.align 3
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.clmul_loop:
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// interleave ldr and pmull(2) for arch which can only issue quadword load every
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// other cycle (i.e. A55)
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ldr q_y0, [x_buf_iter]
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pmull2 v_x0_high.1q, v_x0.2d, v_p4.2d
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ldr q_y1, [x_buf_iter, 16]
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pmull2 v_x1_high.1q, v_x1.2d, v_p4.2d
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ldr q_y2, [x_buf_iter, 32]
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pmull2 v_x2_high.1q, v_x2.2d, v_p4.2d
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ldr q_y3, [x_buf_iter, 48]
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pmull2 v_x3_high.1q, v_x3.2d, v_p4.2d
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pmull v_x0.1q, v_x0.1d, v_p4.1d
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add x_buf_iter, x_buf_iter, 64
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pmull v_x1.1q, v_x1.1d, v_p4.1d
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cmp x_buf_iter, x_buf_end
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pmull v_x2.1q, v_x2.1d, v_p4.1d
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pmull v_x3.1q, v_x3.1d, v_p4.1d
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tbl v_y0.16b, {v_y0.16b}, v_shuffle.16b
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tbl v_y1.16b, {v_y1.16b}, v_shuffle.16b
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tbl v_y2.16b, {v_y2.16b}, v_shuffle.16b
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tbl v_y3.16b, {v_y3.16b}, v_shuffle.16b
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eor v_x0.16b, v_x0.16b, v_x0_high.16b
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eor v_x1.16b, v_x1.16b, v_x1_high.16b
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eor v_x2.16b, v_x2.16b, v_x2_high.16b
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eor v_x3.16b, v_x3.16b, v_x3_high.16b
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eor v_x0.16b, v_x0.16b, v_y0.16b
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eor v_x1.16b, v_x1.16b, v_y1.16b
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eor v_x2.16b, v_x2.16b, v_y2.16b
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eor v_x3.16b, v_x3.16b, v_y3.16b
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bne .clmul_loop
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.endm
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.macro crc32_fold_512b_to_128b
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mov x_tmp, p1_low_b0
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movk x_tmp, p1_low_b1, lsl 16
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fmov d_p1_low, x_tmp
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mov x_tmp2, p1_high_b0
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movk x_tmp2, p1_high_b1, lsl 16
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fmov d_p1_high, x_tmp2
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pmull2 v_tmp_high.1q, v_x0.2d, v_p1.2d
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pmull v_tmp_low.1q, v_x0.1d, v_p1.1d
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eor v_x1.16b, v_x1.16b, v_tmp_high.16b
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eor v_x1.16b, v_x1.16b, v_tmp_low.16b
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pmull2 v_tmp_high.1q, v_x1.2d, v_p1.2d
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pmull v_tmp_low.1q, v_x1.1d, v_p1.1d
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eor v_x2.16b, v_x2.16b, v_tmp_high.16b
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eor v_x2.16b, v_x2.16b, v_tmp_low.16b
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pmull2 v_tmp_high.1q, v_x2.2d, v_p1.2d
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pmull v_tmp_low.1q, v_x2.1d, v_p1.1d
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eor v_x3.16b, v_x3.16b, v_tmp_high.16b
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eor v_x3.16b, v_x3.16b, v_tmp_low.16b
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.endm
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.macro crc64_fold_512b_to_128b
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mov x_tmp, p1_low_b0
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movk x_tmp, p1_low_b1, lsl 16
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movk x_tmp, p1_low_b2, lsl 32
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movk x_tmp, p1_low_b3, lsl 48
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fmov d_p1_low, x_tmp
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mov x_tmp2, p1_high_b0
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movk x_tmp2, p1_high_b1, lsl 16
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movk x_tmp2, p1_high_b2, lsl 32
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movk x_tmp2, p1_high_b3, lsl 48
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fmov d_p1_high, x_tmp2
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pmull2 v_tmp_high.1q, v_x0.2d, v_p1.2d
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pmull v_tmp_low.1q, v_x0.1d, v_p1.1d
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eor v_x1.16b, v_x1.16b, v_tmp_high.16b
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eor v_x1.16b, v_x1.16b, v_tmp_low.16b
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pmull2 v_tmp_high.1q, v_x1.2d, v_p1.2d
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pmull v_tmp_low.1q, v_x1.1d, v_p1.1d
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eor v_x2.16b, v_x2.16b, v_tmp_high.16b
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eor v_x2.16b, v_x2.16b, v_tmp_low.16b
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pmull2 v_tmp_high.1q, v_x2.2d, v_p1.2d
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pmull v_tmp_low.1q, v_x2.1d, v_p1.1d
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eor v_x3.16b, v_x3.16b, v_tmp_high.16b
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eor v_x3.16b, v_x3.16b, v_tmp_low.16b
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.endm
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