mirror of
https://github.com/intel/isa-l.git
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9f75defd57
The relic slver is no longer used for individual versioning on functions and is confusing tools looking for data in text sections. This removes all instances instead of fixing since its usefulness is waining. Fixes #221 Change-Id: Ife0b9f105950a90337c58e8a41ac2cffc0f67d99 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
286 lines
8.0 KiB
NASM
286 lines
8.0 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; gf_3vect_mad_avx(len, vec, vec_i, mul_array, src, dest);
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;;;
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%include "reg_sizes.asm"
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%define PS 8
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%ifidn __OUTPUT_FORMAT__, win64
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%define arg0 rcx
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%define arg0.w ecx
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%define arg1 rdx
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%define arg2 r8
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%define arg3 r9
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%define arg4 r12
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%define arg5 r15
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%define tmp r11
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%define return rax
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%define return.w eax
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%define stack_size 16*10 + 3*8
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%define arg(x) [rsp + stack_size + PS + PS*x]
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%define func(x) proc_frame x
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%macro FUNC_SAVE 0
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sub rsp, stack_size
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vmovdqa [rsp+16*0],xmm6
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vmovdqa [rsp+16*1],xmm7
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vmovdqa [rsp+16*2],xmm8
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vmovdqa [rsp+16*3],xmm9
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vmovdqa [rsp+16*4],xmm10
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vmovdqa [rsp+16*5],xmm11
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vmovdqa [rsp+16*6],xmm12
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vmovdqa [rsp+16*7],xmm13
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vmovdqa [rsp+16*8],xmm14
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vmovdqa [rsp+16*9],xmm15
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save_reg r12, 10*16 + 0*8
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save_reg r15, 10*16 + 1*8
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end_prolog
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mov arg4, arg(4)
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mov arg5, arg(5)
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%endmacro
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%macro FUNC_RESTORE 0
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vmovdqa xmm6, [rsp+16*0]
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vmovdqa xmm7, [rsp+16*1]
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vmovdqa xmm8, [rsp+16*2]
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vmovdqa xmm9, [rsp+16*3]
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vmovdqa xmm10, [rsp+16*4]
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vmovdqa xmm11, [rsp+16*5]
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vmovdqa xmm12, [rsp+16*6]
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vmovdqa xmm13, [rsp+16*7]
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vmovdqa xmm14, [rsp+16*8]
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vmovdqa xmm15, [rsp+16*9]
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mov r12, [rsp + 10*16 + 0*8]
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mov r15, [rsp + 10*16 + 1*8]
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add rsp, stack_size
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%endmacro
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%elifidn __OUTPUT_FORMAT__, elf64
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%define arg0 rdi
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%define arg0.w edi
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%define arg1 rsi
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%define arg2 rdx
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%define arg3 rcx
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%define arg4 r8
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%define arg5 r9
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%define tmp r11
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%define return rax
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%define return.w eax
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%define func(x) x: endbranch
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%define FUNC_SAVE
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%define FUNC_RESTORE
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%endif
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;;; gf_3vect_mad_avx(len, vec, vec_i, mul_array, src, dest)
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%define len arg0
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%define len.w arg0.w
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%define vec arg1
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%define vec_i arg2
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%define mul_array arg3
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%define src arg4
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%define dest1 arg5
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%define pos return
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%define pos.w return.w
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%define dest2 mul_array
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%define dest3 vec_i
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%ifndef EC_ALIGNED_ADDR
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;;; Use Un-aligned load/store
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%define XLDR vmovdqu
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%define XSTR vmovdqu
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%else
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;;; Use Non-temporal load/stor
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%ifdef NO_NT_LDST
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%define XLDR vmovdqa
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%define XSTR vmovdqa
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%else
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%define XLDR vmovntdqa
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%define XSTR vmovntdq
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%endif
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%endif
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default rel
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[bits 64]
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section .text
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%define xmask0f xmm15
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%define xgft1_lo xmm14
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%define xgft1_hi xmm13
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%define xgft2_lo xmm12
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%define xgft2_hi xmm11
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%define xgft3_lo xmm10
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%define xgft3_hi xmm9
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%define x0 xmm0
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%define xtmpa xmm1
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%define xtmph1 xmm2
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%define xtmpl1 xmm3
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%define xtmph2 xmm4
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%define xtmpl2 xmm5
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%define xtmph3 xmm6
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%define xtmpl3 xmm7
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%define xd1 xmm8
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%define xd2 xtmpl1
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%define xd3 xtmph1
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align 16
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mk_global gf_3vect_mad_avx, function
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func(gf_3vect_mad_avx)
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FUNC_SAVE
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sub len, 16
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jl .return_fail
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xor pos, pos
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vmovdqa xmask0f, [mask0f] ;Load mask of lower nibble in each byte
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sal vec_i, 5 ;Multiply by 32
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sal vec, 5
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lea tmp, [mul_array + vec_i]
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vmovdqu xgft1_lo, [tmp] ;Load array Ax{00}, Ax{01}, Ax{02}, ...
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vmovdqu xgft1_hi, [tmp+16] ; " Ax{00}, Ax{10}, Ax{20}, ... , Ax{f0}
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vmovdqu xgft2_lo, [tmp+vec] ;Load array Bx{00}, Bx{01}, Bx{02}, ...
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vmovdqu xgft2_hi, [tmp+vec+16] ; " Bx{00}, Bx{10}, Bx{20}, ... , Bx{f0}
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vmovdqu xgft3_lo, [tmp+2*vec] ;Load array Cx{00}, Cx{01}, Cx{02}, ...
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vmovdqu xgft3_hi, [tmp+2*vec+16]; " Cx{00}, Cx{10}, Cx{20}, ... , Cx{f0}
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mov dest2, [dest1+PS] ; reuse mul_array
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mov dest3, [dest1+2*PS] ; reuse vec_i
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mov dest1, [dest1]
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.loop16:
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XLDR x0, [src+pos] ;Get next source vector
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XLDR xd1, [dest1+pos] ;Get next dest vector
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vpand xtmpa, x0, xmask0f ;Mask low src nibble in bits 4-0
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vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
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vpand x0, x0, xmask0f ;Mask high src nibble in bits 4-0
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; dest1
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vpshufb xtmph1, xgft1_hi, x0 ;Lookup mul table of high nibble
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vpshufb xtmpl1, xgft1_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xtmph1, xtmph1, xtmpl1 ;GF add high and low partials
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vpxor xd1, xd1, xtmph1 ;xd1 += partial
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XLDR xd2, [dest2+pos] ;reuse xtmpl1. Get next dest vector
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XLDR xd3, [dest3+pos] ;reuse xtmph1. Get next dest vector
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; dest2
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vpshufb xtmph2, xgft2_hi, x0 ;Lookup mul table of high nibble
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vpshufb xtmpl2, xgft2_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xtmph2, xtmph2, xtmpl2 ;GF add high and low partials
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vpxor xd2, xd2, xtmph2 ;xd2 += partial
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; dest3
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vpshufb xtmph3, xgft3_hi, x0 ;Lookup mul table of high nibble
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vpshufb xtmpl3, xgft3_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xtmph3, xtmph3, xtmpl3 ;GF add high and low partials
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vpxor xd3, xd3, xtmph3 ;xd3 += partial
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XSTR [dest1+pos], xd1
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XSTR [dest2+pos], xd2
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XSTR [dest3+pos], xd3
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add pos, 16 ;Loop on 16 bytes at a time
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cmp pos, len
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jle .loop16
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lea tmp, [len + 16]
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cmp pos, tmp
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je .return_pass
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.lessthan16:
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;; Tail len
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;; Do one more overlap pass
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mov tmp, len ;Overlapped offset length-16
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XLDR x0, [src+tmp] ;Get next source vector
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XLDR xd1, [dest1+tmp] ;Get next dest vector
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XLDR xd2, [dest2+tmp] ;reuse xtmpl1. Get next dest vector
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XLDR xd3, [dest3+tmp] ;reuse xtmph1. Get next dest vector
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sub len, pos
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movdqa xtmph3, [constip16] ;Load const of i + 16
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vpinsrb xtmpl3, xtmpl3, len.w, 15
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vpshufb xtmpl3, xtmpl3, xmask0f ;Broadcast len to all bytes
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vpcmpgtb xtmpl3, xtmpl3, xtmph3
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vpand xtmpa, x0, xmask0f ;Mask low src nibble in bits 4-0
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vpsraw x0, x0, 4 ;Shift to put high nibble into bits 4-0
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vpand x0, x0, xmask0f ;Mask high src nibble in bits 4-0
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; dest1
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vpshufb xgft1_hi, xgft1_hi, x0 ;Lookup mul table of high nibble
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vpshufb xgft1_lo, xgft1_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xgft1_hi, xgft1_hi, xgft1_lo ;GF add high and low partials
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vpand xgft1_hi, xgft1_hi, xtmpl3
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vpxor xd1, xd1, xgft1_hi
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; dest2
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vpshufb xgft2_hi, xgft2_hi, x0 ;Lookup mul table of high nibble
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vpshufb xgft2_lo, xgft2_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xgft2_hi, xgft2_hi, xgft2_lo ;GF add high and low partials
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vpand xgft2_hi, xgft2_hi, xtmpl3
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vpxor xd2, xd2, xgft2_hi
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; dest3
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vpshufb xgft3_hi, xgft3_hi, x0 ;Lookup mul table of high nibble
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vpshufb xgft3_lo, xgft3_lo, xtmpa ;Lookup mul table of low nibble
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vpxor xgft3_hi, xgft3_hi, xgft3_lo ;GF add high and low partials
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vpand xgft3_hi, xgft3_hi, xtmpl3
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vpxor xd3, xd3, xgft3_hi
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XSTR [dest1+tmp], xd1
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XSTR [dest2+tmp], xd2
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XSTR [dest3+tmp], xd3
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.return_pass:
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mov return, 0
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FUNC_RESTORE
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ret
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.return_fail:
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mov return, 1
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FUNC_RESTORE
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ret
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endproc_frame
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section .data
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align 16
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mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
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constip16:
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dq 0xf8f9fafbfcfdfeff, 0xf0f1f2f3f4f5f6f7
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