mirror of
https://github.com/intel/isa-l.git
synced 2024-12-12 17:33:50 +01:00
1187583a97
- It should be fine to enable pmull always on Apple Silicon - macOS 12+ is required for PMULL instruction. - Changed the conditional macro to __APPLE__ - Rewritten dispatcher using sysctlbyname - Use __USER_LABEL_PREFIX__ - Use __TEXT,__const as readonly section - use ASM_DEF_RODATA macro - fix func decl Change-Id: I800593f21085d8187b480c8bb3ab2bd70c4a6974 Signed-off-by: Taiju Yamada <tyamada@bi.a.u-tokyo.ac.jp>
304 lines
7.6 KiB
ArmAsm
304 lines
7.6 KiB
ArmAsm
/**************************************************************
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Copyright (c) 2019 Huawei Technologies Co., Ltd.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Huawei Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**********************************************************************/
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#include "../include/aarch64_label.h"
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.text
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.global cdecl(gf_vect_dot_prod_neon)
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#ifndef __APPLE__
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.type gf_vect_dot_prod_neon, %function
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#endif
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/* arguments */
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x_len .req x0
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x_vec .req x1
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x_tbl .req x2
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x_src .req x3
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x_dest1 .req x4
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/* returns */
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w_ret .req w0
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/* local variables */
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x_vec_i .req x5
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x_ptr .req x6
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x_pos .req x7
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x_tmp .req x8
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x_tbl1 .req x9
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/* vectors */
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v_gft1_lo .req v0
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v_gft1_hi .req v1
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q_gft1_lo .req q0
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q_gft1_hi .req q1
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v_mask0f .req v2
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q_mask0f .req q2
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v_data_0 .req v8
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v_data_1 .req v9
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v_data_2 .req v10
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v_data_3 .req v11
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v_data_4 .req v12
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v_data_5 .req v13
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v_data_6 .req v14
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v_data_7 .req v15
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q_data_0 .req q8
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q_data_1 .req q9
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q_data_2 .req q10
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q_data_3 .req q11
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q_data_4 .req q12
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q_data_5 .req q13
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q_data_6 .req q14
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q_data_7 .req q15
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v_data_0_lo .req v16
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v_data_1_lo .req v17
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v_data_2_lo .req v18
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v_data_3_lo .req v19
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v_data_4_lo .req v20
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v_data_5_lo .req v21
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v_data_6_lo .req v22
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v_data_7_lo .req v23
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v_data_0_hi .req v_data_0
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v_data_1_hi .req v_data_1
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v_data_2_hi .req v_data_2
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v_data_3_hi .req v_data_3
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v_data_4_hi .req v_data_4
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v_data_5_hi .req v_data_5
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v_data_6_hi .req v_data_6
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v_data_7_hi .req v_data_7
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v_p0 .req v24
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v_p1 .req v25
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v_p2 .req v26
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v_p3 .req v27
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v_p4 .req v28
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v_p5 .req v29
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v_p6 .req v30
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v_p7 .req v31
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q_p0 .req q24
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q_p1 .req q25
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q_p2 .req q26
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q_p3 .req q27
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q_p4 .req q28
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q_p5 .req q29
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q_p6 .req q30
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q_p7 .req q31
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v_p .req v_p0
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q_p .req q_p0
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v_data .req v_p1
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q_data .req q_p1
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v_data_lo .req v_p2
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v_data_hi .req v_p3
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cdecl(gf_vect_dot_prod_neon):
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/* less than 16 bytes, return_fail */
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cmp x_len, #16
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blt .return_fail
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movi v_mask0f.16b, #0x0f
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mov x_pos, #0
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lsl x_vec, x_vec, #3
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.Lloop128_init:
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/* less than 128 bytes, goto Lloop16_init */
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cmp x_len, #128
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blt .Lloop16_init
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/* save d8 ~ d15 to stack */
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sub sp, sp, #64
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stp d8, d9, [sp]
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stp d10, d11, [sp, #16]
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stp d12, d13, [sp, #32]
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stp d14, d15, [sp, #48]
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sub x_len, x_len, #128
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.Lloop128:
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movi v_p0.16b, #0
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movi v_p1.16b, #0
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movi v_p2.16b, #0
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movi v_p3.16b, #0
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movi v_p4.16b, #0
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movi v_p5.16b, #0
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movi v_p6.16b, #0
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movi v_p7.16b, #0
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mov x_tbl1, x_tbl
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mov x_vec_i, #0
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.Lloop128_vects:
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ldr x_ptr, [x_src, x_vec_i]
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add x_vec_i, x_vec_i, #8
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add x_ptr, x_ptr, x_pos
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ldp q_gft1_lo, q_gft1_hi, [x_tbl1], #32
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ldp q_data_0, q_data_1, [x_ptr], #32
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ldp q_data_2, q_data_3, [x_ptr], #32
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ldp q_data_4, q_data_5, [x_ptr], #32
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ldp q_data_6, q_data_7, [x_ptr]
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prfm pldl1keep, [x_tbl1]
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prfm pldl1strm, [x_ptr]
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and v_data_0_lo.16b, v_data_0.16b, v_mask0f.16b
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and v_data_1_lo.16b, v_data_1.16b, v_mask0f.16b
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and v_data_2_lo.16b, v_data_2.16b, v_mask0f.16b
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and v_data_3_lo.16b, v_data_3.16b, v_mask0f.16b
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and v_data_4_lo.16b, v_data_4.16b, v_mask0f.16b
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and v_data_5_lo.16b, v_data_5.16b, v_mask0f.16b
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and v_data_6_lo.16b, v_data_6.16b, v_mask0f.16b
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and v_data_7_lo.16b, v_data_7.16b, v_mask0f.16b
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ushr v_data_0_hi.16b, v_data_0.16b, #4
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ushr v_data_1_hi.16b, v_data_1.16b, #4
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ushr v_data_2_hi.16b, v_data_2.16b, #4
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ushr v_data_3_hi.16b, v_data_3.16b, #4
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ushr v_data_4_hi.16b, v_data_4.16b, #4
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ushr v_data_5_hi.16b, v_data_5.16b, #4
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ushr v_data_6_hi.16b, v_data_6.16b, #4
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ushr v_data_7_hi.16b, v_data_7.16b, #4
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tbl v_data_0_lo.16b, {v_gft1_lo.16b}, v_data_0_lo.16b
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tbl v_data_1_lo.16b, {v_gft1_lo.16b}, v_data_1_lo.16b
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tbl v_data_2_lo.16b, {v_gft1_lo.16b}, v_data_2_lo.16b
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tbl v_data_3_lo.16b, {v_gft1_lo.16b}, v_data_3_lo.16b
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tbl v_data_4_lo.16b, {v_gft1_lo.16b}, v_data_4_lo.16b
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tbl v_data_5_lo.16b, {v_gft1_lo.16b}, v_data_5_lo.16b
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tbl v_data_6_lo.16b, {v_gft1_lo.16b}, v_data_6_lo.16b
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tbl v_data_7_lo.16b, {v_gft1_lo.16b}, v_data_7_lo.16b
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tbl v_data_0_hi.16b, {v_gft1_hi.16b}, v_data_0_hi.16b
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tbl v_data_1_hi.16b, {v_gft1_hi.16b}, v_data_1_hi.16b
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tbl v_data_2_hi.16b, {v_gft1_hi.16b}, v_data_2_hi.16b
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tbl v_data_3_hi.16b, {v_gft1_hi.16b}, v_data_3_hi.16b
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tbl v_data_4_hi.16b, {v_gft1_hi.16b}, v_data_4_hi.16b
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tbl v_data_5_hi.16b, {v_gft1_hi.16b}, v_data_5_hi.16b
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tbl v_data_6_hi.16b, {v_gft1_hi.16b}, v_data_6_hi.16b
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tbl v_data_7_hi.16b, {v_gft1_hi.16b}, v_data_7_hi.16b
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eor v_p0.16b, v_data_0_lo.16b, v_p0.16b
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eor v_p0.16b, v_p0.16b, v_data_0_hi.16b
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eor v_p1.16b, v_data_1_lo.16b, v_p1.16b
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eor v_p1.16b, v_p1.16b, v_data_1_hi.16b
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eor v_p2.16b, v_data_2_lo.16b, v_p2.16b
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eor v_p2.16b, v_p2.16b, v_data_2_hi.16b
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eor v_p3.16b, v_data_3_lo.16b, v_p3.16b
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eor v_p3.16b, v_p3.16b, v_data_3_hi.16b
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eor v_p4.16b, v_data_4_lo.16b, v_p4.16b
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eor v_p4.16b, v_p4.16b, v_data_4_hi.16b
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eor v_p5.16b, v_data_5_lo.16b, v_p5.16b
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eor v_p5.16b, v_p5.16b, v_data_5_hi.16b
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eor v_p6.16b, v_data_6_lo.16b, v_p6.16b
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eor v_p6.16b, v_p6.16b, v_data_6_hi.16b
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eor v_p7.16b, v_data_7_lo.16b, v_p7.16b
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eor v_p7.16b, v_p7.16b, v_data_7_hi.16b
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cmp x_vec_i, x_vec
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blt .Lloop128_vects
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.Lloop128_vects_end:
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add x_ptr, x_dest1, x_pos
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stp q_p0, q_p1, [x_ptr], #32
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stp q_p2, q_p3, [x_ptr], #32
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stp q_p4, q_p5, [x_ptr], #32
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stp q_p6, q_p7, [x_ptr]
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add x_pos, x_pos, #128
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cmp x_pos, x_len
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ble .Lloop128
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.Lloop128_end:
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/* restore d8 ~ d15 */
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ldp d8, d9, [sp]
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ldp d10, d11, [sp, #16]
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ldp d12, d13, [sp, #32]
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ldp d14, d15, [sp, #48]
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add sp, sp, #64
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add x_len, x_len, #128
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cmp x_pos, x_len
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beq .return_pass
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.Lloop16_init:
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sub x_len, x_len, #16
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cmp x_pos, x_len
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bgt .lessthan16_init
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.Lloop16:
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movi v_p.16b, #0
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mov x_tbl1, x_tbl
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mov x_vec_i, #0
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.Lloop16_vects:
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ldr x_ptr, [x_src, x_vec_i]
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ldr q_data, [x_ptr, x_pos]
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add x_vec_i, x_vec_i, #8
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ldp q_gft1_lo, q_gft1_hi, [x_tbl1], #32
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and v_data_lo.16b, v_data.16b, v_mask0f.16b
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ushr v_data_hi.16b, v_data.16b, #4
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tbl v_data_lo.16b, {v_gft1_lo.16b}, v_data_lo.16b
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tbl v_data_hi.16b, {v_gft1_hi.16b}, v_data_hi.16b
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eor v_p.16b, v_data_lo.16b, v_p.16b
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eor v_p.16b, v_p.16b, v_data_hi.16b
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cmp x_vec_i, x_vec
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blt .Lloop16_vects
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.Lloop16_vects_end:
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str q_p, [x_dest1, x_pos]
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add x_pos, x_pos, #16
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cmp x_pos, x_len
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ble .Lloop16
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.Lloop16_end:
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sub x_tmp, x_pos, x_len
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cmp x_tmp, #16
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beq .return_pass
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.lessthan16_init:
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mov x_pos, x_len
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b .Lloop16
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.return_pass:
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mov w_ret, #0
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ret
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.return_fail:
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mov w_ret, #1
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ret
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