mirror of
https://github.com/intel/isa-l.git
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9f75defd57
The relic slver is no longer used for individual versioning on functions and is confusing tools looking for data in text sections. This removes all instances instead of fixing since its usefulness is waining. Fixes #221 Change-Id: Ife0b9f105950a90337c58e8a41ac2cffc0f67d99 Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
195 lines
5.0 KiB
NASM
195 lines
5.0 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;
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;;; gf_vect_mad_sse(len, vec, vec_i, mul_array, src, dest);
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;;;
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%include "reg_sizes.asm"
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%ifidn __OUTPUT_FORMAT__, win64
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%define arg0 rcx
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%define arg0.w ecx
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%define arg1 rdx
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%define arg2 r8
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%define arg3 r9
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%define arg4 r12
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%define arg5 r15
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%define tmp r11
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%define return rax
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%define return.w eax
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%define PS 8
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%define stack_size 16*3 + 3*8
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%define arg(x) [rsp + stack_size + PS + PS*x]
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%define func(x) proc_frame x
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%macro FUNC_SAVE 0
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sub rsp, stack_size
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movdqa [rsp+16*0],xmm6
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movdqa [rsp+16*1],xmm7
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movdqa [rsp+16*2],xmm8
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save_reg r12, 3*16 + 0*8
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save_reg r15, 3*16 + 1*8
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end_prolog
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mov arg4, arg(4)
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mov arg5, arg(5)
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%endmacro
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%macro FUNC_RESTORE 0
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movdqa xmm6, [rsp+16*0]
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movdqa xmm7, [rsp+16*1]
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movdqa xmm8, [rsp+16*2]
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mov r12, [rsp + 3*16 + 0*8]
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mov r15, [rsp + 3*16 + 1*8]
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add rsp, stack_size
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%endmacro
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%elifidn __OUTPUT_FORMAT__, elf64
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%define arg0 rdi
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%define arg0.w edi
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%define arg1 rsi
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%define arg2 rdx
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%define arg3 rcx
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%define arg4 r8
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%define arg5 r9
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%define tmp r11
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%define return rax
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%define return.w eax
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%define func(x) x: endbranch
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%define FUNC_SAVE
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%define FUNC_RESTORE
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%endif
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;;; gf_vect_mad_sse(len, vec, vec_i, mul_array, src, dest)
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%define len arg0
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%define len.w arg0.w
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%define vec arg1
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%define vec_i arg2
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%define mul_array arg3
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%define src arg4
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%define dest arg5
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%define pos return
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%define pos.w return.w
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%ifndef EC_ALIGNED_ADDR
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;;; Use Un-aligned load/store
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%define XLDR movdqu
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%define XSTR movdqu
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%else
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;;; Use Non-temporal load/stor
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%ifdef NO_NT_LDST
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%define XLDR movdqa
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%define XSTR movdqa
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%else
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%define XLDR movntdqa
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%define XSTR movntdq
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%endif
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%endif
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default rel
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[bits 64]
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section .text
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%define xmask0f xmm8
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%define xgft_lo xmm7
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%define xgft_hi xmm6
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%define x0 xmm0
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%define xtmpa xmm1
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%define xtmph xmm2
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%define xtmpl xmm3
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%define xd xmm4
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%define xtmpd xmm5
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align 16
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mk_global gf_vect_mad_sse, function
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func(gf_vect_mad_sse)
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FUNC_SAVE
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sub len, 16
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jl .return_fail
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xor pos, pos
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movdqa xmask0f, [mask0f] ;Load mask of lower nibble in each byte
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sal vec_i, 5 ;Multiply by 32
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movdqu xgft_lo, [vec_i+mul_array] ;Load array Cx{00}, Cx{01}, Cx{02}, ...
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movdqu xgft_hi, [vec_i+mul_array+16] ; " Cx{00}, Cx{10}, Cx{20}, ... , Cx{f0}
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XLDR xtmpd, [dest+len] ;backup the last 16 bytes in dest
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.loop16:
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XLDR xd, [dest+pos] ;Get next dest vector
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.loop16_overlap:
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XLDR x0, [src+pos] ;Get next source vector
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movdqa xtmph, xgft_hi ;Reload const array registers
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movdqa xtmpl, xgft_lo
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movdqa xtmpa, x0 ;Keep unshifted copy of src
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psraw x0, 4 ;Shift to put high nibble into bits 4-0
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pand x0, xmask0f ;Mask high src nibble in bits 4-0
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pand xtmpa, xmask0f ;Mask low src nibble in bits 4-0
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pshufb xtmph, x0 ;Lookup mul table of high nibble
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pshufb xtmpl, xtmpa ;Lookup mul table of low nibble
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pxor xtmph, xtmpl ;GF add high and low partials
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pxor xd, xtmph
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XSTR [dest+pos], xd ;Store result
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add pos, 16 ;Loop on 16 bytes at a time
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cmp pos, len
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jle .loop16
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lea tmp, [len + 16]
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cmp pos, tmp
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je .return_pass
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;; Tail len
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mov pos, len ;Overlapped offset length-16
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movdqa xd, xtmpd ;Restore xd
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jmp .loop16_overlap ;Do one more overlap pass
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.return_pass:
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mov return, 0
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FUNC_RESTORE
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ret
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.return_fail:
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mov return, 1
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FUNC_RESTORE
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ret
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endproc_frame
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section .data
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align 16
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mask0f: dq 0x0f0f0f0f0f0f0f0f, 0x0f0f0f0f0f0f0f0f
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