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6e2013391a
This patch introduces the base, avx and sse optimized zero detect memory function. The zero detect memory function tests if a memory region is all zeroes. If all the bytes in the memory region are zero, the function return a zero. Otherwise, if the memory region has non zero bytes, the zero detect function returns a 1. Change-Id: If965badf750377124d0067d09f888d0419554998 Signed-off-by: John Kariuki <John.K.Kariuki@intel.com>
278 lines
7.7 KiB
Makefile
278 lines
7.7 KiB
Makefile
########################################################################
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# Copyright(c) 2011-2016 Intel Corporation All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# * Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in
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# the documentation and/or other materials provided with the
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# distribution.
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# * Neither the name of Intel Corporation nor the names of its
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# contributors may be used to endorse or promote products derived
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# from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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########################################################################
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objs = \
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bin\ec_base.obj \
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bin\ec_highlevel_func.obj \
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bin\ec_multibinary.obj \
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bin\gf_2vect_dot_prod_avx.obj \
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bin\gf_2vect_dot_prod_avx2.obj \
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bin\gf_2vect_dot_prod_avx512.obj \
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bin\gf_2vect_dot_prod_sse.obj \
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bin\gf_2vect_mad_avx.obj \
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bin\gf_2vect_mad_avx2.obj \
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bin\gf_2vect_mad_avx512.obj \
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bin\gf_2vect_mad_sse.obj \
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bin\gf_3vect_dot_prod_avx.obj \
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bin\gf_3vect_dot_prod_avx2.obj \
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bin\gf_3vect_dot_prod_avx512.obj \
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bin\gf_3vect_dot_prod_sse.obj \
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bin\gf_3vect_mad_avx.obj \
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bin\gf_3vect_mad_avx2.obj \
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bin\gf_3vect_mad_avx512.obj \
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bin\gf_3vect_mad_sse.obj \
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bin\gf_4vect_dot_prod_avx.obj \
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bin\gf_4vect_dot_prod_avx2.obj \
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bin\gf_4vect_dot_prod_avx512.obj \
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bin\gf_4vect_dot_prod_sse.obj \
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bin\gf_4vect_mad_avx.obj \
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bin\gf_4vect_mad_avx2.obj \
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bin\gf_4vect_mad_avx512.obj \
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bin\gf_4vect_mad_sse.obj \
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bin\gf_5vect_dot_prod_avx.obj \
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bin\gf_5vect_dot_prod_avx2.obj \
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bin\gf_5vect_dot_prod_sse.obj \
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bin\gf_5vect_mad_avx.obj \
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bin\gf_5vect_mad_avx2.obj \
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bin\gf_5vect_mad_sse.obj \
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bin\gf_6vect_dot_prod_avx.obj \
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bin\gf_6vect_dot_prod_avx2.obj \
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bin\gf_6vect_dot_prod_sse.obj \
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bin\gf_6vect_mad_avx.obj \
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bin\gf_6vect_mad_avx2.obj \
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bin\gf_6vect_mad_sse.obj \
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bin\gf_vect_dot_prod_avx.obj \
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bin\gf_vect_dot_prod_avx2.obj \
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bin\gf_vect_dot_prod_avx512.obj \
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bin\gf_vect_dot_prod_sse.obj \
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bin\gf_vect_mad_avx.obj \
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bin\gf_vect_mad_avx2.obj \
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bin\gf_vect_mad_avx512.obj \
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bin\gf_vect_mad_sse.obj \
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bin\gf_vect_mul_avx.obj \
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bin\gf_vect_mul_sse.obj \
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bin\pq_check_sse.obj \
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bin\pq_gen_avx.obj \
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bin\pq_gen_avx2.obj \
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bin\pq_gen_avx512.obj \
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bin\pq_gen_sse.obj \
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bin\raid_base.obj \
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bin\raid_multibinary.obj \
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bin\xor_check_sse.obj \
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bin\xor_gen_avx.obj \
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bin\xor_gen_avx512.obj \
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bin\xor_gen_sse.obj \
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bin\crc16_t10dif_01.obj \
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bin\crc16_t10dif_by4.obj \
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bin\crc16_t10dif_copy_by4.obj \
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bin\crc32_ieee_01.obj \
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bin\crc32_ieee_by4.obj \
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bin\crc32_iscsi_00.obj \
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bin\crc32_iscsi_01.obj \
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bin\crc64_base.obj \
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bin\crc64_ecma_norm_by8.obj \
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bin\crc64_ecma_refl_by8.obj \
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bin\crc64_iso_norm_by8.obj \
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bin\crc64_iso_refl_by8.obj \
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bin\crc64_jones_norm_by8.obj \
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bin\crc64_jones_refl_by8.obj \
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bin\crc64_multibinary.obj \
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bin\crc_base.obj \
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bin\adler32_base.obj \
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bin\crc_multibinary.obj \
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bin\huff_codes.obj \
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bin\hufftables_c.obj \
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bin\igzip.obj \
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bin\igzip_base.obj \
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bin\igzip_body.obj \
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bin\igzip_decode_block_stateless_01.obj \
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bin\igzip_decode_block_stateless_04.obj \
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bin\igzip_finish.obj \
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bin\flatten_ll.obj \
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bin\encode_df.obj \
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bin\encode_df_04.obj \
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bin\proc_heap.obj \
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bin\igzip_icf_body_h1_gr_bt.obj \
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bin\igzip_icf_finish.obj \
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bin\igzip_icf_base.obj \
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bin\igzip_inflate.obj \
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bin\igzip_inflate_multibinary.obj \
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bin\igzip_multibinary.obj \
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bin\igzip_update_histogram_01.obj \
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bin\igzip_update_histogram_04.obj \
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bin\rfc1951_lookup.obj \
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bin\crc32_gzip_refl_by8.obj \
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bin\adler32_sse.obj \
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bin\adler32_avx2_4.obj \
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bin\igzip_deflate_hash.obj \
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bin\igzip_gen_icf_map_lh1_04.obj \
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bin\igzip_gen_icf_map_lh1_06.obj \
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bin\igzip_set_long_icf_fg_04.obj \
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bin\igzip_set_long_icf_fg_06.obj \
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bin\igzip_icf_body.obj \
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bin\mem_zero_detect_avx.obj \
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bin\mem_zero_detect_base.obj \
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bin\mem_multibinary.obj \
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bin\mem_zero_detect_sse.obj
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INCLUDES = -I./ -Ierasure_code/ -Iraid/ -Icrc/ -Iigzip/ -Iinclude/ -Imem/
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LINKFLAGS = /nologo
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CFLAGS = -O2 -D NDEBUG /nologo -D_USE_MATH_DEFINES -Qstd=c99 $(INCLUDES) $(D)
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AFLAGS = -f win64 $(INCLUDES) $(D)
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CC = icl
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AS = yasm
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lib: bin static dll
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static: bin isa-l_static.lib
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dll: bin isa-l.dll
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bin: ; -mkdir $@
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isa-l_static.lib: $(objs)
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lib -out:$@ @<<
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$?
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<<
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isa-l.dll: $(objs)
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link -out:$@ -dll -def:isa-l.def @<<
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$?
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<<
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{erasure_code}.c.obj:
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$(CC) $(CFLAGS) /c -Fo$@ $?
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{erasure_code}.asm.obj:
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$(AS) $(AFLAGS) -o $@ $?
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{raid}.c.obj:
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$(CC) $(CFLAGS) /c -Fo$@ $?
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{raid}.asm.obj:
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$(AS) $(AFLAGS) -o $@ $?
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{crc}.c.obj:
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$(CC) $(CFLAGS) /c -Fo$@ $?
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{crc}.asm.obj:
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$(AS) $(AFLAGS) -o $@ $?
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{igzip}.c.obj:
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$(CC) $(CFLAGS) /c -Fo$@ $?
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{igzip}.asm.obj:
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$(AS) $(AFLAGS) -o $@ $?
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{mem}.c.obj:
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$(CC) $(CFLAGS) /c -Fo$@ $?
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{mem}.asm.obj:
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$(AS) $(AFLAGS) -o $@ $?
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# Examples
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ex = xor_example.exe crc_simple_test.exe crc64_example.exe igzip_example.exe igzip_sync_flush_example.exe
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ex: lib $(ex)
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$(ex): $(@B).obj
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.obj.exe:
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link /out:$@ $(LINKFLAGS) isa-l.lib $?
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# Check tests
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checks = \
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gf_vect_mul_test.exe \
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erasure_code_test.exe \
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gf_inverse_test.exe \
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erasure_code_update_test.exe \
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xor_gen_test.exe \
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pq_gen_test.exe \
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xor_check_test.exe \
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pq_check_test.exe \
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crc16_t10dif_test.exe \
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crc16_t10dif_copy_test.exe \
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crc32_funcs_test.exe \
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crc64_funcs_test.exe \
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igzip_wrapper_hdr_test.exe \
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igzip_rand_test.exe \
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mem_zero_detect_test.exe
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checks: lib $(checks)
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$(checks): $(@B).obj
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check: $(checks)
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!$?
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# Unit tests
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tests = \
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gf_vect_mul_base_test.exe \
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gf_vect_dot_prod_base_test.exe \
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gf_vect_dot_prod_test.exe \
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gf_vect_mad_test.exe \
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erasure_code_base_test.exe
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tests: lib $(tests)
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$(tests): $(@B).obj
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# Performance tests
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perfs = \
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gf_vect_mul_perf.exe \
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gf_vect_mul_sse_perf.exe \
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gf_vect_mul_avx_perf.exe \
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gf_vect_dot_prod_sse_perf.exe \
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gf_vect_dot_prod_avx_perf.exe \
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gf_2vect_dot_prod_sse_perf.exe \
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gf_3vect_dot_prod_sse_perf.exe \
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gf_4vect_dot_prod_sse_perf.exe \
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gf_5vect_dot_prod_sse_perf.exe \
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gf_6vect_dot_prod_sse_perf.exe \
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gf_vect_dot_prod_perf.exe \
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gf_vect_dot_prod_1tbl.exe \
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gf_vect_mad_perf.exe \
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erasure_code_perf.exe \
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erasure_code_base_perf.exe \
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erasure_code_sse_perf.exe \
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erasure_code_update_perf.exe \
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xor_gen_perf.exe \
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pq_gen_perf.exe \
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crc16_t10dif_perf.exe \
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crc32_ieee_perf.exe \
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crc32_iscsi_perf.exe \
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igzip_perf.exe \
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igzip_sync_flush_perf.exe \
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crc32_gzip_refl_perf.exe \
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mem_zero_detect_perf.exe
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perfs: lib $(perfs)
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$(perfs): $(@B).obj
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clean:
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-if exist *.obj del *.obj
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-if exist bin\*.obj del bin\*.obj
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-if exist isa-l_static.lib del isa-l_static.lib
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-if exist *.exe del *.exe
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-if exist isa-l.lib del isa-l.lib
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-if exist isa-l.dll del isa-l.dll
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zlib.lib:
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igzip_inflate_perf.exe: zlib.lib
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igzip_inflate_test.exe: zlib.lib
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