isa-l/erasure_code/gf_vect_gfni.inc
Pablo de Lara 1eff12dddb erasure_code: implement EC with AVX512 + GFNI
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2023-11-23 10:56:28 +00:00

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; Copyright(c) 2023 Intel Corporation All rights reserved.
;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Multiply 1 source register to up to 6 different GF table registers
; and XOR the results to partial registers
;
%macro GF_MUL_XOR 4-19
%define %%SRC %1
%define %%GFTABLE1 %2
%define %%TMP1 %3
%define %%PARTIAL1 %4
%define %%GFTABLE2 %5
%define %%TMP2 %6
%define %%PARTIAL2 %7
%define %%GFTABLE3 %8
%define %%TMP3 %9
%define %%PARTIAL3 %10
%define %%GFTABLE4 %11
%define %%TMP4 %12
%define %%PARTIAL4 %13
%define %%GFTABLE5 %14
%define %%TMP5 %15
%define %%PARTIAL5 %16
%define %%GFTABLE6 %17
%define %%TMP6 %18
%define %%PARTIAL6 %19
%define %%N_BLOCKS ((%0 - 1) / 3)
%assign %%I 1
%rep %%N_BLOCKS
vgf2p8affineqb %%TMP %+ %%I, %%SRC, %%GFTABLE %+ %%I, 0x00
%assign %%I (%%I + 1)
%endrep
%assign %%I 1
%rep %%N_BLOCKS
vpxorq %%PARTIAL %+ %%I, %%TMP %+ %%I
%assign %%I (%%I + 1)
%endrep
%endmacro